Medium Block Lengths Research Articles

Performance of polar codes with low complexity cyclic redundancy check aided bit‐flipping for successive cancellation list decoding over power line channels

SummaryPower lines have complex transmission characteristics and noise interference when used as information transmission channel, thus limiting their data‐carrying rate and reliability. Impulsive noise is the most dominant factor degrading the performance of communication systems over power lines. To combat the impulsive noise, polar codes are introduced into the orthogonal frequency division multiplexing (OFDM)‐based power line communication (PLC) system. Because the successive cancelation list bit‐flip (SCLF) decoding algorithm of polar codes has high decoding complexity, a low complexity segmented cyclic redundancy check (CRC)‐aided SCLF decoding is proposed to improve the decoding performance. The decoding process can be terminated early with segmented CRC, which can reduce the bit‐flip decoding complexity significantly with short and medium block lengths. Experimental results demonstrate that for various configurations, the proposed decoder outperforms the traditional CRC‐aided SCL decoder in terms of decoding performance and complexity, and the suggested polar codes‐based OFDM‐based PLC system can reduce the bit error rate of the system in the presence of impulsive noise.

Bidirekciono stek dekodovanje polarnih kodova

Introduction/purpose: The paper introduces a reduced latency stack decoding algorithm of polar codes, inspired by the bidirectional stack decoding of convolutional codes and based on the folding technique. Methods: The stack decoding algorithm (also known as stack search) that is useful for decoding tree codes, the list decoding technique introduced by Peter Elias and the folding technique for polar codes which is used to reduce the latency of the decoding algorithm. The simulation was done using the Monte Carlo procedure. Results: A new polar code decoding algorithm, suitable for parallel implementation, is developed and the simulation results are presented. Conclusions: Polar codes are a class of capacity achieving codes that have been adopted as the main coding scheme for control channels in 5G New Radio. The main decoding algorithm for polar codes is the successive cancellation decoder. This algorithm performs well at large blocklengths with a low complexity, but has very low reliability at short and medium blocklengths. Several decoding algorithms have been proposed in order to improve the error correcting performance of polar codes. The successive cancellation list decoder, in conjunction with a cyclic redundancy check, provides very good error-correction performance, but at the cost of a high implementation complexity. The successive cancellation stack decoder provides similar error-correction performance at a lower complexity. Future machine-type and ultra reliable low latency communication applications require high-speed low latency decoding algorithms with good error correcting performance. In this paper, we propose a novel decoding algorithm, inspired by the bidirectional stack decoding of classical convolutional codes, with reduced latency that achieves similar performance as the classical successive cancellation list and successive cancellation stack decoding algorithms. The results are presented analytically and verified by simulation.

Distributed video coding using interval overlapped arithmetic coding

Distributed video coding (DVC) is a flexible and novel video coding mode that is different from traditional video compression methods, which can shift the complex task such as motion estimation from encoder to decoder. Nowadays, most of the DVC architectures adopt channel coding such as low-density parity-check codes. It is found that arithmetic coding can be also extended to compress correlated sources and even has better performance than the channel coding for short to medium block length sources. Therefore, we propose a DVC scheme using interval overlapped arithmetic coding that is distributed arithmetic coding (DAC) without feedback channel, where the Key frames are compressed using traditional video coder while the Wyner–Ziv frames are compressed using DAC. We compare the rate–distortion performance of the proposed scheme with the state-of-the-arts, and the experimental results indicate that the proposed scheme is competitive. The source code for this scheme is available in GitHub.

Repetition‐assisted decoding of polar codes

Error correction performance of finite-length polar codes has been a major concern in the past decade. This Letter presents a method for improving the error correction performance of cyclic redundancy check (CRC)-aided successive cancellation list decoding for polar codes of medium block-lengths with high code rates. In the proposed decoding scheme, a one-time repetition of least reliable bit-channels along with partial protection of the message is employed to correct the error(s) when decoding fails. The results show an improvement of nearly 0.2 dB in error correction performance.

A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic

This paper proposes a high-throughput energy-efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in such architectures to provide a favorable tradeoff between throughput and energy efficiency at short to medium block lengths. At longer block lengths, the paper proposes a hybrid-logic SC decoder that combines the advantageous aspects of the combinational decoder with the low-complexity nature of sequential-logic decoders. Performance characteristics on ASIC and FPGA are presented with a detailed power consumption analysis for combinational decoders. Finally, the paper presents an analysis of the complexity and delay of combinational decoders, and of the throughput gains obtained by hybrid-logic decoders with respect to purely synchronous architectures.

Jointly optimized rate-compatible UEP-LDPC codes for half-duplex co-operative relay networks

This paper addresses the design of low-density parity-check (LDPC) codes for half-duplex co-operative relay networks. Structured rate-compatible codes with unequal error protection (UEP) are designed through joint optimization of the codes for the channels between source and relay and source and destination. The proposed codes clearly outperform simpler LDPC codes which are not optimized for relay channels and puncturing-based rate-compatible LDPC codes, and they show a significant performance improvement over the direct link communication depending on the position of relay. The optimization algorithm for the proposed codes is based on density evolution using the Gaussian approximation and optimal variable node degree distributions are found through iterative linear programming. Interestingly, they anyhow show performance which is almost comparable to the performance of codes optimized through a more complex non-linear optimization algorithm. We analyze the performance of our proposed codes with short, medium and long block lengths, and with low and high rates under realistic assumptions, i.e., imperfect decoding of the codeword at relay and variant signal-to-noise ratio within a single codeword.

Ordered statistics-based list decoding techniques for linear binary block codes

The ordered statistics-based list decoding techniques for linear binary block codes of small to medium block length are investigated. The construction of a list of the test error patterns is considered. The original ordered-statistics decoding (OSD) is generalized by assuming segmentation of the most reliable independent positions (MRIPs) of the received bits. The segmentation is shown to overcome several drawbacks of the original OSD. The complexity of the ordered statistics-based decoding is further reduced by assuming a partial ordering of the received bits in order to avoid the complex Gauss elimination. The probability of the test error patterns in the decoding list is derived. The bit error rate performance and the decoding complexity trade-off of the proposed decoding algorithms is studied by computer simulations. Numerical examples show that, in some cases, the proposed decoding schemes are superior to the original OSD in terms of both the bit error rate performance as well as the decoding complexity.

Early stopping for the iterative decoding for Q-LDPC

Q-ary low-density parity-check (Q-LDPC) codes have a better performance than those of the binary low-density parity-check (B-LDPC) codes, at short and medium block lengths, but the decoder of Q-LDPC has more complexity. In this article, a new stop criterion is proposed. By analyzing the changes of the maximum posteriori probability of the variable node, the criterion decides whether the iteration of the decoder must be stopped. The simulation results show that the stop criterion can effectively reduce the computation complexity of the Q-LDPC decoder with negligible performance loss.

Distributed Arithmetic Coding

We propose a distributed binary arithmetic coder for Slepian-Wolf coding with decoder side information, along with a soft joint decoder. The proposed scheme provides several advantages over existing schemes, and its performance is equal to or better than that of an equivalent scheme based on turbo codes at short and medium block lengths.

An Ensemble of Iteratively Decodable Codes Constructed Based on a Superposition Method

In this paper, the construction of new families of error-correcting codes adapted from Boutros and Lentmaier's generalized low-density (GLD) codes, which we called generalized irregular low-density (GILD) codes, is investigated. By introducing irregular base matrices, significant improvements on Boutros and Lentmaier's results are achieved. Two cases are considered; in the first case, the same constituent code is used, and in the second case, different constituent codes are used. It is proved by an ensemble performance argument that these codes exist and are asymptotically good in the sense of the minimum-distance criterion. It is also proved that the performance of GILD codes approaches the binary symmetric channel capacity limit. Iterative decoding of GILD codes for communication over an additive white Gaussian noise channel is also studied. The high flexibility in selecting the parameters of GILD codes and their better performance and higher rate make them more attractive than GLD codes, and hence, suitable for small and medium block lengths forward-error-correcting schemes. Comparisons of simulation results between some GILD codes and some good low-density parity-check codes show very close performances

Nonlinear programming approaches to decoding low-density parity-check codes

We consider the decoding problem for low-density parity-check codes, and apply nonlinear programming methods. This extends previous work using linear programming (LP) to decode linear block codes. First, a multistage LP decoder based on the branch-and-bound method is proposed. This decoder makes use of the maximum-likelihood-certificate property of the LP decoder to refine the results when an error is reported. Second, we transform the original LP decoding formulation into a box-constrained quadratic programming form. Efficient linear-time parallel and serial decoding algorithms are proposed and their convergence properties are investigated. Extensive simulation studies are performed to assess the performance of the proposed decoders. It is seen that the proposed multistage LP decoder outperforms the conventional sum-product (SP) decoder considerably for low-density parity-check (LDPC) codes with short to medium block length. The proposed box-constrained quadratic programming decoder has less complexity than the SP decoder and yields much better performance for LDPC codes with regular structure

GGD Model of Extrinsic Information With Dynamic Parameter Assignment for Turbo Decoder

This letter proposes a strategy using a generalized Gaussian distribution (GGD) to characterize the extrinsic information generated from the constituent maximum a posteriori (MAP) decoders in order to improve the performance of an iterative turbo decoder for finite block lengths. A matching technique based on the measured moments and distance criterion is introduced to dynamically select the appropriate parameters of the GGD model for the extrinsic information in each iteration. The simulation results indicate that the proposed strategy can offer performance gain in medium block lengths over both additive white Gaussian noise and Rayleigh-fading channels.