The high performance of an elliptic curve (EC) crypto system depends efficiently on the arithmetic in the underlying finite field. We have to propose and compare three levels of Galois Field <svg style="vertical-align:-2.3205pt;width:58.950001px;" id="M1" height="18.799999" version="1.1" viewBox="0 0 58.950001 18.799999" width="58.950001" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,15.85)"><path id="x47" d="M692 302v-28q-45 -6 -54.5 -17t-9.5 -55v-86q0 -62 7 -95q-7 -2 -32 -7.5l-37 -8l-35.5 -7.5t-40.5 -7t-38.5 -4t-40.5 -2q-165 0 -266 93t-101 243q0 84 32 151t86 108t121.5 63t142.5 22q29 0 62.5 -4t52 -7.5t47.5 -10.5t31 -7l15 -156l-28 -6q-17 87 -66.5 121.5
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l-26 -65h-233z" /></g><g transform="matrix(.012,-0,0,-.012,46.673,7.688)"><use xlink:href="#x36"/></g> <g transform="matrix(.017,-0,0,-.017,53.012,15.85)"><use xlink:href="#x29"/></g> </svg>. The proposed architecture is based on Lopez-Dahab elliptic curve point multiplication algorithm, which uses Gaussian normal basis for <svg style="vertical-align:-2.3205pt;width:58.950001px;" id="M4" height="18.799999" version="1.1" viewBox="0 0 58.950001 18.799999" width="58.950001" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,15.85)"><use xlink:href="#x47"/></g><g transform="matrix(.017,-0,0,-.017,12.217,15.85)"><use xlink:href="#x46"/></g><g transform="matrix(.017,-0,0,-.017,21.209,15.85)"><use xlink:href="#x28"/></g><g transform="matrix(.017,-0,0,-.017,27.091,15.85)"><use xlink:href="#x32"/></g> <g transform="matrix(.012,-0,0,-.012,35.25,7.688)"><use xlink:href="#x31"/></g><g transform="matrix(.012,-0,0,-.012,40.961,7.688)"><use xlink:href="#x36"/></g><g transform="matrix(.012,-0,0,-.012,46.673,7.688)"><use xlink:href="#x33"/></g> <g transform="matrix(.017,-0,0,-.017,53.012,15.85)"><use xlink:href="#x29"/></g> </svg> field arithmetic. The proposed <svg style="vertical-align:-2.3205pt;width:58.950001px;" id="M5" height="18.725" version="1.1" viewBox="0 0 58.950001 18.725" width="58.950001" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,15.775)"><use xlink:href="#x47"/></g><g transform="matrix(.017,-0,0,-.017,12.217,15.775)"><use xlink:href="#x46"/></g><g transform="matrix(.017,-0,0,-.017,21.209,15.775)"><use xlink:href="#x28"/></g><g transform="matrix(.017,-0,0,-.017,27.091,15.775)"><use xlink:href="#x32"/></g> <g transform="matrix(.012,-0,0,-.012,35.25,7.613)"><use xlink:href="#x31"/></g><g transform="matrix(.012,-0,0,-.012,40.961,7.613)"><use xlink:href="#x39"/></g><g transform="matrix(.012,-0,0,-.012,46.673,7.613)"><use xlink:href="#x33"/></g> <g transform="matrix(.017,-0,0,-.017,53.012,15.775)"><use xlink:href="#x29"/></g> </svg> is based on an efficient Montgomery add and double algorithm, also the Karatsuba-Ofman multiplier and Itoh-Tsujii algorithm are used as the inverse component. The hardware design is based on optimized finite state machine (FSM), with a single cycle 193 bits multiplier, field adder, and field squarer. The another proposed architecture <svg style="vertical-align:-2.3205pt;width:58.950001px;" id="M6" height="18.799999" version="1.1" viewBox="0 0 58.950001 18.799999" width="58.950001" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,15.85)"><use xlink:href="#x47"/></g><g transform="matrix(.017,-0,0,-.017,12.217,15.85)"><use xlink:href="#x46"/></g><g transform="matrix(.017,-0,0,-.017,21.209,15.85)"><use xlink:href="#x28"/></g><g transform="matrix(.017,-0,0,-.017,27.091,15.85)"><use xlink:href="#x32"/></g> <g transform="matrix(.012,-0,0,-.012,35.25,7.688)"><use xlink:href="#x32"/></g><g transform="matrix(.012,-0,0,-.012,40.961,7.688)"><use xlink:href="#x35"/></g><g transform="matrix(.012,-0,0,-.012,46.673,7.688)"><use xlink:href="#x36"/></g> <g transform="matrix(.017,-0,0,-.017,53.012,15.85)"><use xlink:href="#x29"/></g> </svg> is based on applications for which compactness is more important than speed. The FPGA’s dedicated multipliers and carry-chain logic are used to obtain the small data path. The different optimization at the hardware level improves the acceleration of the ECC scalar multiplication, increases frequency and the speed of operation such as key generation, encryption, and decryption. Finally, we have to implement our design using Xilinx XC4VLX200 FPGA device.
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