MB SRAM Research Articles

A grand spread estimator using a graphics processing unit

The spread of a source is defined as the number of distinct destinations to which the source has sent packets during a measurement period. Spread estimation is essential in traffic monitoring, measurement, intrusion detection, to mention a few. To support high speed networking, recent research suggests implementing a spread estimator in fast but small on-chip memory such as SRAM. A state-of-the-art estimator can hold succinct information about 10 million distinct packets using 1 MB SRAM. This implies that a measurement period should restart whenever every 10 million distinct packets fill up the SRAM. Spread estimation is a challenging problem because two spread values from different measurement periods cannot be aggregated to derive the total value. Therefore, current spread estimators have a serious limitation concerning the length of the measurement period because SRAM is available a few megabytes at most. In this paper, we propose a spread estimator that utilizes a large memory space of a graphics processing unit on a commodity PC. The proposed estimator utilizes a 1 GB memory, a hundred times larger than those of current spread estimators, and its throughput is still around 160 Gbps. According to our experiments, the proposed scheme can cover a measurement period of a few dozen hours while the current state-of-the-art can cover only one hour. To the best of our knowledge, this has not been achieved by any spread estimators thus far.

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-change memory (PCM) can provide much larger storage capacity than traditional main memories. A key challenge for enabling high-performance and scalable hybrid memories, though, is efficiently managing the metadata (e.g., tags) for data cached in DRAM at a fine granularity. Based on the observation that storing metadata off-chip in the same row as their data exploits DRAM row buffer locality, this paper reduces the overhead of fine-granularity DRAM caches by only caching the metadata for recently accessed rows on-chip using a small buffer. Leveraging the flexibility and efficiency of such a fine-granularity DRAM cache, we also develop an adaptive policy to choose the best granularity when migrating data into DRAM. On a hybrid memory with a 512MB DRAM cache, our proposal using an 8KB on-chip buffer can achieve within 6% of the performance of, and 18% better energy efficiency than, a conventional 8MB SRAM metadata store, even when the energy overhead due to large SRAM metadata storage is not considered.

A Self-Timed SRAM Design for Average-Case Performance

This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.

3D-Integrated SRAM Components for High-Performance Microprocessors

3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication involves stacking two or more die connected with a very high density and low-latency interface. The die-to-die vias that comprise this interface can be treated as regular on-chip metal due to their small size (on the order of 1 mum) and high speed (sub-FO4 die-to-die communication delay). The increased device density and the ability to place and route in the third dimension provide new opportunities for microarchitecture design. In this paper, we focus on the 3D-integrated designs of SRAM structures. We show that the dense die-to-die vias enable 3D-integrated SRAM components that are partitioned at the level of individual wordlines or bitlines. This results in a wire length reduction within SRAM arrays, and a reduction in the area footprint, which reduces the wires required for global routing. The wire length reduction provides simultaneous latency and energy reduction benefits, e.g., 47 percent latency reduction and 18 percent energy reduction for a 4 MB 4-die stacked 3D SRAM array. A 3D implementation of a 128-entry multiported SRAM array achieves a 36 percent latency improvement with a simultaneous energy reduction of 55 percent. As planar designs adapt high-performance techniques such as hierarchical wordlines to improve performance, 3D integration provides even larger benefits, making it a desirable technology for high-performance designs. For the 4 MB SRAM array, the 3D-integrated designs provide additional latency reduction benefit over the planar designs when hierarchical wordlines are implemented in both planar and 3D designs.

Design and optimization of large size and low overhead off-chip caches

Large off-chip L3 caches can significantly improve the performance of memory-intensive applications. However, conventional L3 SRAM caches are facing two issues as those applications require increasingly large caches. First, an SRAM cache has a limited size due to the low density and high cost of SRAM and, thus, cannot hold the working sets of many memory-intensive applications. Second, since the tag checking overhead of large caches is nontrivial, the existence of L3 caches increases the cache miss penalty and may even harm the performance of some memory-intensive applications. To address these two issues, we present a new memory hierarchy design that uses cached DRAM to construct a large size and low overhead off-chip cache. The high density DRAM portion in the cached DRAM can hold large working sets, while the small SRAM portion exploits the spatial locality appearing in L2 miss streams to reduce the access latency. The L3 tag array is placed off-chip with the data array, minimizing the area overhead on the processor for L3 cache, while a small tag cache is placed on-chip, effectively removing the off-chip tag access overhead. A prediction technique accurately predicts the hit/miss status of an access to the cached DRAM, further reducing the access latency. Conducting execution-driven simulations for a 2 GHz 4-way issue processor and with 11 memory-intensive programs from the SPEC 2000 benchmark, we show that a system with a cached DRAM of 64 MB DRAM and 128 KB on-chip SRAM cache as the off-chip cache outperforms the same system with an 8 MB SRAM L3 off-chip cache by up to 78 percent measured by the total execution time. The average speedup of the system with the cached-DRAM off-chip cache is 25 percent over the system with the L3 SRAM cache.

Integration Of BPDA-PDA Polyimide With Two Levels Of Al(Cu) Interconnects

AbstractAs device geometries continue to scale down, a larger portion of the circuit delay is contributed by interconnects, and the majority of this delay is due to capacitive loading. The replacement of plasma-deposited SiO2 as an intermetal dielectric with an insulator of lower dielectric constant can provide performance improvement through the reduction of capacitance.A commercially available polyimide, BiPhenylene DiAnhydride – Phenylene DiAmine, BPDA-PDA, with an out-of-plane dielectric constant 3.0, is evaluated by integration with AI(Cu) in a double level metal, BiCMOS 4MB SRAM device, with 0.5μm groundrules. Process challenges unique to integration of an organic rather than inorganic insulator are described and experimental features concerning process integration, particularly via etch, Al(Cu) deposition, adhesion and moisture management are presented.

Sub-0.5 µm Lithography Using an Excimer Laser at 248 nm

The advent of deep ultra-violet (DUV) lithography using an excimer laser stepper at 248 nm has extended the capability of photolithography in achieving sub-0.5 µm resolution required for the fabrication of 64MB DRAM and 16MB SRAM. This paper reports on the progress of our DUV R&D efforts in working toward this goal. To qualify the stepper, electrical wafer probing was found effective in providing a large volume of data with high sensitivity, accuracy, and precision in the measurements. Advanced resist materials based on the chemical amplification principle demonstrated good sub-0.5 µm resolution, excellent sensitivity, and good etch selectivity required for DUV lithography. However, resist processes for both the positive and negative tone materials still require further optimization incorporating the use of anti-reflective coatings (ARC). Spin-on organic ARC has proven feasible in eliminating both thin-film interference effects and reflective notching. DUV lithography promises to be a strong contender for the next generation of ULSI fabrication, where the limiting factor may lie in the high cost of advanced resist and ARC materials.

Effect of the PI9000/9200 charge neutralization system on advanced device characteristics

The analytical and production tools available to a process engineer on PI9000/9200 high current implanters, to overcome charging, are discussed. A selection of device results are presented. A correlation of in situ charge monitoring system with device yield/test structure breakdown voltage is demonstrated. The effect on advanced device probe yields and reliability measurements are investigated. It is found that devices up to 4 MB DRAM and 1 MB SRAM, show a flat probe yield response to electron flood gun emission current. It is shown that the device lifetime testing yield can be affected by over-flooding.