MB DRAM Research Articles

Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance

Phase change RAM (PRAM) is an emerging memory technology that has fast read access time, low standby power, and high storage density. Multi-level Cell (MLC) PRAM has even higher storage density but suffers from low reliability and long write latency. This paper investigates a set of cost-effective design solutions for enabling MLC PRAM to be used as a mainstream memory technology. Earlier, we had proposed a multi-level scheme to improve reliability through circuit level and architecture level tuning—the corresponding scheme is referred to as baseline. In this paper, we show how tuning the programming current profile at the device level helps reduce the error rates even further and enables the use of an even lower cost error control coding (ECC) to achieve the same level of reliability. We use a PRAM + DRAM hybrid memory configuration to analyze the tradeoffs between programming energy, IPC, and memory lifetime. We show that for the SPEC2006 and DeCapo benchmarks, a hybrid memory designed with 1 GB PRAM and 8 MB DRAM can achieve either longer lifetime or lower energy (compared to the baseline scheme) by tuning the programming current profile. For instance, if a BCH ( t = 2) ECC unit is used, we can increase RESET programming pulse width to enhance memory lifetime by a factor of 10; for a fixed memory lifetime constraint of 106 PRAM WRITE cycles, we can tune the programming current profile to achieve 27 percent memory energy saving with no loss in IPC.

A high-throughput and high-capacity IPv6 routing lookup system

With the growing number of routing entries, IP routing lookup has become the major performance bottleneck in backbone routers. In this paper, a complete hardware-based routing lookup system is proposed to achieve high-throughput and high-capacity for IPv6. The proposed system is a cache-centric, hash-based architecture that contains a routing lookup application specific integrated circuit (ASIC) and a memory set. A hash function is used to reduce lookup time for the routing table and ternary content addressable memory (TCAM) effectively resolves the collision problem. The gate count of the ASIC, excluding the binary content addressable memory (BCAM), is about 5306 gates, using an in-house 0.18μm CMOS single-poly six-metal standard cell library. The results of post-layout simulations show that the ASIC operates in 3.6ns so that the routing lookup system approaches 260 Mega lookups per second (Mlps), which is sufficient for 100Gbps networks. The memory density is good, with each routing entry requiring only 64bits. Moreover, the routing table only needs 10.24KB on-chip BCAM, 20.04KB off-chip TCAM and 29.29MB DRAM for 3.6M routing entries in the proposed system.

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-change memory (PCM) can provide much larger storage capacity than traditional main memories. A key challenge for enabling high-performance and scalable hybrid memories, though, is efficiently managing the metadata (e.g., tags) for data cached in DRAM at a fine granularity. Based on the observation that storing metadata off-chip in the same row as their data exploits DRAM row buffer locality, this paper reduces the overhead of fine-granularity DRAM caches by only caching the metadata for recently accessed rows on-chip using a small buffer. Leveraging the flexibility and efficiency of such a fine-granularity DRAM cache, we also develop an adaptive policy to choose the best granularity when migrating data into DRAM. On a hybrid memory with a 512MB DRAM cache, our proposal using an 8KB on-chip buffer can achieve within 6% of the performance of, and 18% better energy efficiency than, a conventional 8MB SRAM metadata store, even when the energy overhead due to large SRAM metadata storage is not considered.

Scalable Packet Classification for Enabling Internet Differentiated Services

Nowadays, IP networks are rapidly evolving toward a QoS-enabled infrastructure. The need for packet classification is increasing in accordance with emerging differentiated services. While the new differentiated services could significantly increase the number of rules, it has been demonstrated that performing packet classification on a potentially large number of rules is difficult and has poor worst-case performance. In this work, we present an enhanced pruning search algorithm called tuple pruning plus (TPP) for packet classification, which outperforms the existing schemes on the scalability. Our main idea is to simplify the lookup procedure and to avoid unnecessary probing by maintaining the least-cost property of rule through precomputation and the proposed information marker. With extra rules added for information marker, only one access is required in each packet classification. In our experiments, 70 MB DRAM is used to achieve 50 million packets per second (MPPS) for a 1 M-rule set, showing a performance improvement by a factor of 50. We also present a heuristic to further reduce the required storage to about 20 MB. These results demonstrate the effectiveness of the TPP scheme to achieve high speed packet classification

Design and optimization of large size and low overhead off-chip caches

Large off-chip L3 caches can significantly improve the performance of memory-intensive applications. However, conventional L3 SRAM caches are facing two issues as those applications require increasingly large caches. First, an SRAM cache has a limited size due to the low density and high cost of SRAM and, thus, cannot hold the working sets of many memory-intensive applications. Second, since the tag checking overhead of large caches is nontrivial, the existence of L3 caches increases the cache miss penalty and may even harm the performance of some memory-intensive applications. To address these two issues, we present a new memory hierarchy design that uses cached DRAM to construct a large size and low overhead off-chip cache. The high density DRAM portion in the cached DRAM can hold large working sets, while the small SRAM portion exploits the spatial locality appearing in L2 miss streams to reduce the access latency. The L3 tag array is placed off-chip with the data array, minimizing the area overhead on the processor for L3 cache, while a small tag cache is placed on-chip, effectively removing the off-chip tag access overhead. A prediction technique accurately predicts the hit/miss status of an access to the cached DRAM, further reducing the access latency. Conducting execution-driven simulations for a 2 GHz 4-way issue processor and with 11 memory-intensive programs from the SPEC 2000 benchmark, we show that a system with a cached DRAM of 64 MB DRAM and 128 KB on-chip SRAM cache as the off-chip cache outperforms the same system with an 8 MB SRAM L3 off-chip cache by up to 78 percent measured by the total execution time. The average speedup of the system with the cached-DRAM off-chip cache is 25 percent over the system with the L3 SRAM cache.

Environmental impacts of microchip manufacture

Environmental impacts associated with the manufacture of semiconductor devices are characterized from two perspectives: a qualitative survey of key issues and quantitative analysis of energy and entropy associated with the processes in the production chain. The main issues of environmental concern are emissions from fabs, health effects on line workers and high energy and material use. Results of analysis of material use in the production chain suggest that total weight of secondary fossil fuel and chemical inputs to produce and use a single 2-g 32MB DRAM chip are 1600 and 72 g, respectively. Secondary inputs of fossil fuels to manufacture a chip total 600 times its weight, high compared to a factor of 1–2 for an automobile or refrigerator. Due to its extremely low-entropy, organized structure, the materials intensity of a microchip is orders of magnitude higher than that of “traditional” goods.

Post-Anneal Stress Reduction of 200 mm Silicon Wafers in Single Wafer Rapid Thermal Annealing

ABSTRACTIn every wafer processing step wafer stress management is extremely important for advanced device manufacturing. Thermally induced stress on device wafers has a large impact on lithography and affects device yield. Thermally induced stress during rapid thermal annealing (RTA) steps in high density 512MB DRAM device fabrication was investigated using a lamp-based (cold wall) RTA system and compared to results using a furnace-based (hot wall) single wafer RTA system. Compared to the lamp-based (cold wall) system, RTA in a furnace-based (hot wall) system was found to be very effective in suppressing thermally induced stress and increasing device yield due to superior pattern transfer characteristics in lithography.

The 1.7 kilogram microchip: energy and material use in the production of semiconductor devices.

The scale of environmental impacts associated with the manufacture of microchips is characterized through analysis of material and energy inputs into processes in the production chain. The total weight of secondary fossil fuel and chemical inputs to produce and use a single 2-gram 32MB DRAM chip are estimated at 1600 g and 72 g, respectively. Use of water and elemental gases (mainly N2) in the fabrication stage are 32,000 and 700 g per chip, respectively. The production chain yielding silicon wafers from quartz uses 160 times the energy required for typical silicon, indicating that purification to semiconductor grade materials is energy intensive. Due to its extremely low-entropy, organized structure, the materials intensity of a microchip is orders of magnitude higher than that of "traditional" goods. Future analysis of semiconductor and other low entropy high-tech goods needs to include the use of secondary materials, especially for purification.

Single chip dual-issue risc processor for real-time MPEG-2 software decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.

Single Chip Dual---Issue RISC Processor for Real---Time MPEG---2 Software Decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.

The manufacture of rim phase shiftin reticles

Abstract RIM Phase Shifting is one of a number of Phase Shifting Techniques being considered to bring potential advantages of improved resolution and better process latitude to optical projection printing in the volume production of high density MB DRAMS with minimum feature sizes down to 0.3μm(1,2,3). This paper describes a production process developed under the ISL project capable of manufacturing rim shifted PSMs for use at g line, i line and DUV wavelengths. The formidable issues of inspection and repair for all types of PSMs are not discussed. The ISL technique uses quartz substrate Reactive Ion Etching, (R.I.E) for the phase shift, and wet chrome etching for the production of the rim. Optical and E-beam resists were used for reticle manufacture.

Further developments in surface imaging resists.

At present one of the most promising production-worthy 193nm resist approaches is a single layer, dry developed, surface imaging, silylation process. An evaluation of commercially available developmental resists shows excellent process versatility and lithographic performance. An evaluation of silylation conditions shows more versatility than previously demonstrated. No flow is seen in silylated features, leading to excellent dimensional control and edge profiles. Preliminary results indicate better than 0.18μm resolution and linearity to 0.20μm without the use of phase shift masks. Geometries of 0.1μm have been demonstrated in a resist process which is available for evaluation of 0.20μm devices processes as well as 256MB DRAM circuits.

Hexafluoroacetone in resist chemistry

Photo‐and radiation‐sensitive materials are used are resists in the fabrication of memory and logic devices. The 64 MB DRAMs, scchedules for 1995, will requre feature sizes below 0.5 μm (see figure). Deep‐UV lithography is a promising method of achieving these targets meaning that new resists with faovrable transmission and bleaching characteristics in this spectral region are required. magnified image

Sub-0.5 µm Lithography Using an Excimer Laser at 248 nm

The advent of deep ultra-violet (DUV) lithography using an excimer laser stepper at 248 nm has extended the capability of photolithography in achieving sub-0.5 µm resolution required for the fabrication of 64MB DRAM and 16MB SRAM. This paper reports on the progress of our DUV R&D efforts in working toward this goal. To qualify the stepper, electrical wafer probing was found effective in providing a large volume of data with high sensitivity, accuracy, and precision in the measurements. Advanced resist materials based on the chemical amplification principle demonstrated good sub-0.5 µm resolution, excellent sensitivity, and good etch selectivity required for DUV lithography. However, resist processes for both the positive and negative tone materials still require further optimization incorporating the use of anti-reflective coatings (ARC). Spin-on organic ARC has proven feasible in eliminating both thin-film interference effects and reflective notching. DUV lithography promises to be a strong contender for the next generation of ULSI fabrication, where the limiting factor may lie in the high cost of advanced resist and ARC materials.

Effect of the PI9000/9200 charge neutralization system on advanced device characteristics

The analytical and production tools available to a process engineer on PI9000/9200 high current implanters, to overcome charging, are discussed. A selection of device results are presented. A correlation of in situ charge monitoring system with device yield/test structure breakdown voltage is demonstrated. The effect on advanced device probe yields and reliability measurements are investigated. It is found that devices up to 4 MB DRAM and 1 MB SRAM, show a flat probe yield response to electron flood gun emission current. It is shown that the device lifetime testing yield can be affected by over-flooding.

Thermal Strain Measurements in Electronic Packages Through Fractional Fringe Moire´ Interferometry

Fractional Fringe Moire´ Interferometry (FFMI)—a new experimental methodology to measure accurately deformations and consequently strains—has been successfully implemented to determine thermally induced strains in a specimen made from an AT&T 1MB DRAM device. The specimen was heated uniformly from room temperature to 90° C. Resulting moire´ fringe patterns were recorded, analyzed using digital-image-processing and in plane displacements in the device were determined. Strain components were computed by simple differentiation of the displacement fields. The technique proved to be successful in detecting full displacement fields with submicron resolution. Contour maps showing actual thermo/mechanical strain components in the specimen were constructed. Those maps can provide an excellent tool realistic for strain analysis of microelectronic devices regardless of the structural and material complexity.

Electron beam lithography: Its applications

This paper addresses the various aspects of e-beam lithography as they relate to device fabrication at and below 0.25 μm. These dimensions will eventually be necessary for the fabrication of 256 MB DRAM chips. It is important to evaluate how key components in lithography have to be integrated to provide this necessary early learning. E-beam lithography tools today may consist of Gaussian round and variable shape beam systems. The understanding of the performance of the tool goes hand in hand with directly related issues such as electron-resist interaction, proximity effect correction, etc. Since each of these parameters can be optimized independently, but not simultaneously as a complete set, tradeoffs will have to be made. The discussion will therefore focus on compromises between critical issues such as beam profile, throughput, image quality, process latitude, degree of accuracy in proximity effect correction, and overall process engineering for very high resolution lithography. All of these aspects are strategically important components in support of device technology research. The implementation of an ‘‘integrated e-beam lithography’’ operation as it relates to fully scaled and partially scaled device programs will be discussed. Current work on device fabrication below 0.25 μm demonstrates the capability of integration of all sectors of e-beam lithography to provide early research work for ULSI device technology.