Maze Routing Algorithm Research Articles

Postrouting Optimization of the Working Clock Frequency of Single-Flux-Quantum Circuits

With the emergence of large-scale single-flux-quantum (SFQ) circuits, it is desirable to offload heavy routing tasks to automated electronic design automation (EDA) tools. The unique characteristic of SFQ circuits is that large clock distribution networks are generally required to pass the clock signal to clocked cells subject to limited fanout drive capability of the intervening clock buffers. This scenario results in a huge challenge to control the clock skew and minimize the signal path delays in an SFQ circuit during the routing step. Values of the clock skew and path delays determine not only the maximum working frequencies but also whether or not there are hold time violations. However, it is not necessary to develop a timing-driven routing tool specifically for SFQ circuits from scratch because the number of the paths that set the maximum clock frequencies or give rise to hold time violations is generally very small. Thus, we present a novel postrouting optimization framework that augments standard maze routing tools by adding the capability of reducing path lengths to maximize the working frequency of the chip and meandering paths to avoid hold time violations. A framework is developed in which machine learning is applied to analyze wire distributions and a maze routing algorithm is used to reroute targeted paths. Based on the MIT-LL SFQ5ee process technology, we demonstrate that our framework can improve the minimum working frequency by 7$\%$ on average over the state-of-the-art EDA routing tool for a suite of 14 SFQ circuits while fixing all hold time violations.

QGDR: A Via-Minimization-Oriented Routing Tool for Large-Scale Superconductive Single-Flux-Quantum Circuits

Single-flux-quantum (SFQ) circuit technologies are promising digital circuit technologies with high-speed and extremely low-power characteristics. However, heavy wire routing tasks are finished either by considerable human effort or by commercial routing tools with few physical considerations for the SFQ circuits. In this paper, we present an integrated global and detailed router for the SFQ circuits, qGDR, which aims at reducing the impedance mismatch during signal transfer by minimizing the total number of used vias. The global router allocates routing resources while minimizing the via usage by a dynamic layer assignment algorithm. The detailed router follows the global routing results to complete the routing task by resorting to a maze routing algorithm. Following the MIT-LL SFQ5ee process technology, qGDR can use only two routing layers to route an 8-bit integer divider with more than 40 000 Josephson junctions in less than one hour.

Algorithms for Maze Routing With Exact Matching Constraints

Exact route matching is an important constraint for analog and mixed signal designs with nonuniform metal stacks. In this paper, we propose a constrained-path-based maze routing algorithm that can handle exact matching constraints for multiple nets. We also propose a scalable framework that utilizes the proposed maze routing algorithm for realistic problem sizes. Compared to the pattern routing algorithms proposed recently , our algorithms allow a more thorough exploration of the solution space by allowing bends to be inserted to avoid congested regions. Furthermore, we propose an ILP-based model to explore the impact of the initial routing topologies on the final solutions. Our experimental study demonstrates that the proposed algorithm leads to significant reductions in congestion costs compared to the previous algorithm.

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules

Due to process limitations, wiring rules are imposed on chip layout by foundries. Under nanometer wiring rules, the required separation between two wire ends is dependent on their surrounding wires, and there is a limit on the minimum length of each wire segment. However, traditional shortest path algorithms are not properly designed for these rules. In the paper, we propose a maze routing algorithm, called MANA, capable of finding legal shortest paths under these rules. Experiments with seven industrial cases show that by handling these rules during maze routing, 94% of the violations are prevented on average, and the overall runtime of a commercial router is reduced by 71%. In addition, the total wire length is also reduced by 3% on average.

Optimal Path Planning for Mobile Robot Navigation

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Some optimal path planning algorithms for navigating mobile rectangular robot among obstacles and weighted regions are presented. The approach is based on a higher geometry maze routing algorithm. Starting from a top view of a workspace with obstacles, the so-called free workspace is first obtained by virtually expanding the obstacles in the image. After that, an 8-geomerty maze routing algorithm is applied to obtain an optimal collision-free path with linear time and space complexities. The proposed methods cannot only search an optimal path among various terrains but also find an optimal path for the 2-D piano mover's problem with 3 DOF. Furthermore, the algorithm can be easily extended to the dynamic collision avoidance problem among multiple autonomous robots or path planning in the 3-D space. </para>

Full-Chip Routing Considering Double-Via Insertion

As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the postlayout stage. The increasing design complexity, however, leaves very limited space for postlayout optimization. It is thus desirable to consider the double-via insertion at both the routing and postrouting stages. In this paper, we present a new full-chip gridless routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies a novel two-pass, bottom-up routability-driven routing framework and features a new redundant-via aware detailed maze routing algorithm (which could be applied to both gridless and grid-based routing). We also propose a graph-matching based post-layout double-via insertion algorithm to achieve a higher insertion rate. In particular, the algorithm is optimal for grid-based routing with up to three routing layers and the stacked-via structure. Experiments show that our methods significantly improve the via count, number of dead vias, double-via insertion rates, and running times.

Multilevel Routing With Redundant Via Insertion

This brief presents an improved multilevel full-chip routing system which integrates the redundant via placement in the routing flow for yield and reliability enhancement. The system features a pre-coarsening stage which is equipped with fast congestion-driven L-pattern global router followed by detailed router. The L-pattern global routing benefits to the reduction of vias and thus relieves the burden of redundant via addition. In addition, a rvia-driven maze routing algorithm is also integrated in the system to improve the insertion of redundant vias. Finally a redundant via placement heuristic is adopted to enhance the completion rate. We have tested the system on a set of commonly used benchmark circuits and compared the results with a previous multilevel routing system. Besides much enhancement obtained in the aspect of redundant via placement, the system also obtains high routing completion rate, minimized total wire length and total number of vias in satisfactory runtime

A Method for Searching Optimal Routes with Collision Avoidance on Raster Charts

Collision avoidance is an intensive discussion issue for navigation safety. This article introduces a new routing algorithm for finding optimal routes with collision detection and avoidance on raster charts or planes. After the required data structure of the raster chart is initialized, the maze routing algorithm is applied to obtain the particular route of each ship. Those ships that have potential to collide will be detected by simulating the particular routes with ship domains. The collision avoidance scheme can be achieved by using the collision-area-marking method with collision avoidance rules at sea. The algorithm has linear time and space complexities, and is sufficiently fast to perform real-time routing on the raster charts.

Via design rule consideration in multilayer maze routing algorithms

Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules. In this paper, we show that finding an optimal route of a two-pin net in a multilayer routing environment under practical via design rules can be surprisingly difficult. A straightforward extension to the maze routing algorithm that disallows via-rule incorrect routes may either cause a suboptimal route to be found, or more seriously, cause the failure to find any route even if one exists. We present a refined heuristic to this problem by embedding the distance to the most recently placed via in an extended connection graph so that the maze routing algorithm has a higher chance of finding a via-rule correct optimum path in the extended connection graph. We further present efficient data-structures to implement the maze routing algorithm without the need to preconstruct the extended connection graph. Experimental results confirmed the usefulness of our algorithm and its applicability to a wide range of CMOS technologies.

A gridless multilayer router for standard cell circuits using CTM cells

We present a gridless multilayer router suitable for standard cell circuits using central terminal model (CTM) cells. A CTM cell has pins in the middle which split the over-the-cell (OTC) routing region into top and bottom parts. Nets are routed in both the channel (if needed) and OTC by using a channel router. Our router uses a combined constraint graph and tile expansion algorithm. We report the first maze router to take advantage of a graph based algorithm to solve the net ordering problem. Unlike a laggard pure maze router, it has the time efficiency of a fast graph based algorithm and the better results of a maze routing algorithm. This is also the first report of the use of a tile expansion maze router for the variable height routing problem. By variable height routing we mean that a single execution of the routing algorithm will result in a completely routed solution. The only thing that is not determined a priori is the height or number of tracks needed. Our router achieves channelless solutions for the Primary1 circuit by routing over the cell in three layers. It also generates equal or better results compared to the best of the previous channel routers for all the examples we have tried. In fact, Sockeye is the first router to achieve density solutions for the r1, r3, and r4 examples for two layers and for the r3 example for three layers.

General-purpose parallel hardware approach to the routing problem of VLSI layout

A novel solution to the important problem of speeding up the routing process in integrated circuit (IC) design, involving the use of general-purpose parallel computing hardware, is introduced. In the past, attempts to speed up any one stage of the VLSI design process have often resulted in a very expensive, dedicated piece of hardware which cannot be used to speed up other phases of the design process. In the case of routing, dedicated hardware has been designed to accelerate specifically the maze routing algorithm, which is more useful for routing PCBs rather than VLSI designs. As more general-purpose parallel hardware has become available, especially in the form of workstations, there has been an increasing need to exploit parallelism in many computationally intensive applications. The paper addresses the problem of exploiting parallelism in the computationally intensive problem of routing for VLSI design. This is performed hierarchically and involves two stages: global and detailed routing. A parallel routing framework was proposed to fit into such a structure. Not only some of the ideas in the framework but also a general evaluation of the different parts of the framework are presented.

Parallel maze routing on hypercube computers

The routing problem of VLSI layout design is computationally very expensive because of the inherent complexity of the task. Consequently, with the trend to increasing complexity of VLSI circuits, the routing phase threatens to become a major bottleneck in the design process. Resorting to parallel processing to remedy this situation is a viable alternative. The paper proposes a parallel maze routing algorithm that is targeted to run on loosely coupled multiprocessor systems such as hypercubes.

K-dTree based Gridless Maze Routing on Message Passing Multiprocessor Systems

The routing of nets or a set of interconnection points is a compute intensive application encountered in CAD for VLSI design. In this paper, we propose a gridless algorithm for area routing based on the Hightower's Maze routing algorithm for message passing multiprocessor systems. The suitability of k-d trees as a data structuring technique for gridless maze routing is established. Since segments of routes are stored as rectangular objects in the k-d tree, the algorithm facilitates routing with variable width conductor paths. Results obtained both through simulation techniques and those obtained on an actual multiprocessor system based on message passing exhibit speedup proportional to the number of processors in the multiprocessor system.

Maze routing on a hypercube multicomputer

The implementation of Lee's maze routing algorithm on an MIMD hypercube multiprocessor computer can follow several plausible mappings and synchronization strategies. These are evaluated experimentally on an NCUBE/7 hypercube computer with 64 processors. Different grid partitioning and mapping strategies result in a different balance between computation and communication time. The total routing time is significantly impacted by the synchronization and termination detection scheme used. Further, by rearranging the computation, it is possible to overlap much of the interprocessor communication with the computation and realize a significant reduction in the overall run time. By choosing the right partitioning and synchronization scheme and by overlapping computation and communication, a good speedup is obtained on large routing grids.

An automatic cell pattern generation system for CMOS transistor-pair array LSI

In an automatic layout design system for masterslice or gate array LSI, a cell library must be provided in advance. Manual preparation of such a cell library requires a considerable amount of design effort and turnaround time. In this paper, an automatic cell pattern generation algorithm and its program implementation for a CMOS transistor-pair array masterslice are presented. The cell pattern generation process consists of the transistor-pair extraction, transistor-pair placement and routing phases. The transistor-pair placement method is based on an iterative improvement algorithm for wiring congestion. For the wiring phase, Lee's maze routing algorithm is modified for application to polysilicon, diffusion and two aluminum layers. Furthermore, a new interconnection ordering algorithm is proposed and its effectiveness for attaining higher wireability is experimentally shown. Finally, it is shown that the proposed cell pattern generation system achieves a significant reduction of cell pattern design time compared to conventional manual design.

Knowledge Representation and Utilization for Optimal Route Search

A guidance method for route search with knowledge is developed by combining knowledge representation and utilization in the frame form with an enumeration algorithm. The knowledge-guided route search introduced is based on three key techniques: obstacle-adaptive spatial cells, direct and automatic application of routing knowledge to the path-finding process, and an extended maze routing algorithm.