Maximum Lattice Temperature Research Articles

Single-event burnout in β-Ga2O3 Schottky barrier diode induced by high-energy proton

Single-Event Burnout (SEB) can cause hard damage to devices, leading to permanent failure. However, previous studies have rarely explored the effects of high-energy proton irradiation-induced SEB in β-Ga2O3 Schottky Barrier Diode (SBD), and the underlying mechanisms remain largely unexplored. Experimental results indicate that the reverse bias voltage during irradiation is a critical factor influencing the failure of β-Ga2O3 SBD. Compared to 300 MeV proton irradiation without bias, the introduction of a 300 V reverse bias voltage results in a significant reduction in forward current density (JF). When the reverse bias voltage reaches 400 V or higher, the 300 MeV proton induces SEB in the device. The SEM image of the damaged region reveals that the irradiated device has “voids” formed due to the melting of the Ga2O3 material. Geant 4 and TCAD simulation results indicate that the burnout phenomenon is caused by the elevated lattice temperature inside the device, which results from the implantation of secondary particles under a high reverse bias voltage. As the reverse bias voltage increases, the maximum lattice temperature of β-Ga2O3 SBD also rises. When the reverse bias voltage is sufficiently high, the local lattice temperature inside the device reaches the melting point of Ga2O3 material, ultimately leading to SEB.

A machine learning approach to accelerate reliability prediction in nanowire FETs from self-heating perspective

Nanowire Field Effect Transistors (NWFETs) have been considered as the next-generation technology for sub-10 nm technology nodes, succeeding FinFETs. However, the highly confined nature of Nanowire FETs creates reliability issues that significantly impact their performance. Therefore, this work proposes a machine learning-based technique for analyzing the self-heating-induced reliability issues in NWFETs. The influence of self-heating effects in NWFET has been predicted in terms of saturation current (Idsat), threshold voltage (Vth), the maximum carrier temperature along the channel (eTmax), and the maximum Lattice temperature (LTmax) with multivariable regression. TCAD-assisted machine learning has been used for algorithm training and prediction. A dataset has been created by varying the parameters of the NWFETs like the thickness of the channel (tsi), the thickness of oxide (tox), Length of source/drain (Lsd), length of source/drain contact (Lsdc), doping concentrations etc. The Random Forest Regression algorithm has been used to estimate the performance of NWFETs in predicting the desired output parameters suitably with the given dataset.

Modelling thermal energy transfer in a femtosecond pulsed laser ablation of metal using a coupled spring-mass oscillator

Femtosecond pulsed laser ablation (fs-PLA) is an interesting yet complicated field of study especially for undergraduate students entering the field. Hence, a bridging concept using classical and mechanical analog will be helpful. In this paper, we modelled the thermal energy transfer between electron and lattice system in a fs-PLA of metal described by two temperature model (TTM) using a coupled spring-mass oscillator. This was achieved by providing correspondence of TTM parameters to the coupled spring-mass oscillator, with temperature as position, electron thermal conductivity as coefficient of friction, electron-phonon coupling factor as spring term, electron/lattice heat capacity as the mass m 1/m 2 respectively, and laser source term as the driving force. The thermophysical properties considered are temperature dependent leading to position dependent parameters of coupled spring-mass oscillator. Results showed that the coupled spring-mass oscillator exhibit many behavior similar to the TTM. Additionally, maximum positions achieved by m 2 behave similarly with maximum lattice temperature after achieving certain threshold value. However, many features of TTM such as spatial dependence and crater formation are not observed in the coupled spring-mass oscillator. Despite its limitation, the coupled spring-mass oscillator model was able to represent many features of the thermal energy transfer of fs-PLA, and could be an easy and useful model in understanding fs-PLA.

4H-SiC layer with multiple trenches in lateral double-diffused metal-oxide-semiconductor transistors for high temperature and high voltage applications

In this paper, we present a novel lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor for high-temperature and high breakdown voltage applications. The key idea in our study is replacing a 4H-SiC layer in a part of the buried oxide region (BOX) to reduce temperature effects. Moreover, the top of the 4H-SiC layer has multiple trenches to increase the breakdown voltage. These multiple trenches have been filled with an N-type silicon material. So, we call the proposed structures as multiple trenches 4H-SiC LDMOS (MTSiC-LDMOS). The proposed device is simulated by a two-dimensional ATLAS simulator, and we have shown that the maximum lattice temperature decreases and the breakdown voltage improves by optimization of multiple trenches in the 4H-SiC region. Also, the results show that the current flow and specific on-resistance have improved. Therefore, the MTSiC-LDMOS structure is more reliable than a conventional LDMOS (C-LDMOS) for high-temperature and high breakdown voltage applications.

Effect of sample temperature on femtosecond laser ablation of copper

We conduct an experimental study supported by theoretical analysis of single laser ablating copper to investigate the interactions between laser and material at different sample temperatures, and predict the changes of ablation morphology and lattice temperature. For investigating the effect of sample temperature on femtosecond laser processing, we conduct experiments on and simulate the thermal behavior of femtosecond laser irradiating copper by using a two-temperature model. The simulation results show that both electron peak temperature and the relaxation time needed to reach equilibrium increase as initial sample temperature rises. When the sample temperature rises from 300 K to 600 K, the maximum lattice temperature of the copper surface increases by about 6500 K under femtosecond laser irradiation, and the ablation depth increases by 20%. The simulated ablation depths follow the same general trend as the experimental values. This work provides some theoretical basis and technical support for developing femtosecond laser processing in the field of metal materials.

Simulation Studies on Single-Event Effects and the Mechanisms of SiC VDMOS from a Structural Perspective.

The single-event effect reliability issue is one of the most critical concerns in the context of space applications for SiC VDMOS. In this paper, the SEE characteristics and mechanisms of the proposed deep trench gate superjunction (DTSJ), conventional trench gate superjunction (CTSJ), conventional trench gate (CT), and conventional planar gate (CT) SiC VDMOS are comprehensively analyzed and simulated. Extensive simulations demonstrate the maximum SET current peaks of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS, which are 188 mA, 218 mA, 242 mA, and 255 mA, with a bias voltage VDS of 300 V and LET = 120 MeV·cm2/mg, respectively. The total charges of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS collected at the drain are 320 pC, 1100 pC, 885 pC, and 567 pC, respectively. A definition and calculation of the charge enhancement factor (CEF) are proposed. The CEF values of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS are 43, 160, 117, and 55, respectively. Compared with CTSJ-, CT-, and CP SiC VDMOS, the total charge and CEF of the DTSJ SiC VDMOS are reduced by 70.9%, 62.4%, 43.6% and 73.1%, 63.2%, and 21.8%, respectively. The maximum SET lattice temperature of the DTSJ SiC VDMOS is less than 2823 K under the wide operating conditions of a drain bias voltage VDS ranging from 100 V to 1100 V and a LET value ranging from 1 MeV·cm2/mg to 120 MeV·cm2/mg, while the maximum SET lattice temperatures of the other three SiC VDMOS significantly exceed 3100 K. The SEGR LET thresholds of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS are approximately 100 MeV·cm2/mg, 15 MeV·cm2/mg, 15 MeV·cm2/mg, and 60 MeV·cm2/mg, respectively, while the value of VDS = 1100 V.

Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance

Nanosheet Field Effect Transistor (NSFET) has emerged as a promising candidate to replace FinFET devices at sub-7nm technology nodes and for different SoC applications. In this work, we have investigated the DC properties of 3D vertically-stacked NSFET including the impact of self-heating effect (SHE) and also influence of geometry scaling. The thermal resistance and the maximum lattice temperature have been analyzed according to the device’s channel number. Also, the distribution of lattice temperature has been exposed. During the 3D investigation, it has been observed that SHE degrades the switching performance and subthreshold swing SS ≈ 22%. Furthermore, it is found that the proposed device is showing improved figure of merits as ION (∼2.77 × 10−5A), IOFF (∼10−20A), SS (>60 mV decade−1) and ION/IOFF (∼1015). The DIBL has been reduced by −52% when the NS’s width is ranging from 10 to 5 nm, and increased from 32 to 92 mV V−1 when the gate-length decreases from 14 to 8 nm.

The Effect of Different Pulse Widths on Lattice Temperature Variation of Silicon under the Action of a Picosecond Laser.

In laser processing, due to the short interaction time between an ultrashort pulse laser and silicon, it has been difficult to study the lattice temperature change characteristics of silicon. In this paper, the interaction between a picosecond laser and silicon was studied. Based on the Fokker–Planck equation and two-temperature model (TTM) equation, a simulation model of silicon heating by different pulse-width picosecond lasers was established. The results show that within the range of 15 to 5 ps, the maximum lattice temperature tended to increase first and then decrease with the decreasing pulse width. The watershed was around 7.5 ps. The model error was less than 3.2% when the pulse width was 15 ps and the single pulse energy was 25 μJ.

Damage mechanism of SiC Schottky barrier diode irradiated by heavy ions

In this paper, the failure mode and mechanism of silicon carbide (SiC) Schottky barrier diode (SBD) irradiated by high-energy tantalum (Ta) ions are studied. The experimental results show that the reverse bias voltage during irradiation is the key factor causing the failure of SiC SBDs. When the reverse bias of the device is 400 V, the heavy ions will cause the single event burnout (SEB), and a “hole” formed by the melting of SiC material appears in the irradiated device. When the reverse bias is 250–300 V, the failure is manifested as the off state leakage current increases with the ion fluence. The higher the bias voltage of the device, the higher the leakage increase rate caused by heavy ions. For the devices with increased leakage, the leakage channels caused by heavy ions are found in the whole active region, based on microscopic analysis. The TCAD simulation results show that the incidence of heavy ions will lead the lattice temperature to increase in the device, and the maximum lattice temperature increases with bias voltage increasing. When the bias voltage is large enough, the local lattice temperature inside the device reaches the melting point of SiC material, resulting in SEB. When the bias voltage is relatively low, the lattice temperature is lower than the melting point of SiC material, so it will not cause burnout. However, the maximum lattice temperature in the device is concentrated near the Schottky junction, and the melting point of Schottky metal is much lower than that of SiC material. This may lead the Schottky junction to damage locally and eventually produce leakage path.

Using Hetro-Structure Window in Nano Scale Junctionless SOI MOSFET for High Electrical Performance

A new junctionless MOS transistor is proposed in this paper using hetro-structure technology. A T-shape SiGe is applied under the source and channel region to extend the depletion region in the device. The Si(1−x)Gex region with a mole fraction of x = 0.3 for the germanium, changes the surface potential of the device due to the different band gap than silicon. Off-current in the proposed SiGe region in buried oxide of Junctionless SOI-MOSFET (SG-JLMOS) reduces significantly as it is compared to the Conventional Junctionless SOI-MOSFET (C-JLMOS). Also, using a window with higher thermal capability than silicon dioxide reduces maximum lattice temperature in the active region. In this situation, the reliability of the device increases and the better performance of the transistor is achieved in high temperature. Our simulation with 2D ATLAS simulator shows that DIBL and subthreshold swing have lower values in the proposed SG-JLMOS. So, short channel effects which are the vital parameters in the nano scale device are controlled, considerably.

A computational study of heat transfer and material removal in picosecond laser micro-grooving of copper

A 2D two-temperature model (TTM) is developed for picosecond laser micro-grooving of copper (Cu) and discretized using the finite difference scheme, to explore the temperature evolution and groove formation process. For lattice and electron subsystems, as well as the coupling strength between them, comprehensive temperature-dependent properties are employed and updated in real time to make the calculation more accurate. The model verification is then conducted and a reasonable good agreement has been found between predicted and measured groove depths. Using the verified model, computational studies of temperature field evolution are carried out in different fluence levels. For low fluence of around 0.283 J/cm2, phase change can be neglected, and the temperature difference between two subsystems decreases with an increase in pulse width and can be neglected when the pulse width is over 200 ps. In contrast, for high fluence of about 10.61 J/cm2, the maximum lattice temperature increases rapidly to boiling point within 3 ps, and the peak electron temperature is around 10 times higher, leading to material removal via evaporation. Under this high fluence level, groove depth around 0.25 μm is obtained within a 12 ps single pulse irradiation. In addition, thermal diffusion occurs from the residual hot zone adjacent to groove edge towards surrounding area during the off-pulse period, as the heat affected zone depth is up to 1 μm after 500 ps and over 4 μm after 6 ns, and the peak residual lattice temperature drops to about 396 K from boiling point within 53 ns. Moreover, the groove depth and groove profile show a periodically evolving manner with respect to scanning times, and for each scanning, a slow-fast-slow pattern has been observed in groove depth increase and profile development.

A Simple Proposal to Reduce Self-heating Effect in SOI MOSFETs

In this work, we aim to design a silicon on insulator MOSFET in which the self-heating effect is fully removed. Within the proposed scheme, a T-shaped 4H-SiC region is embedded in the buried oxide layer, extended from the silicon drift region towards the substrate providing a heating pathway to improve the low thermal conductivity of the oxide. This T-shaped 4H-SiC part can absorb heat from the active region and transfer it to the substrate area. Therefore, heat dissipation rising from the high gate and drain bias in MOSFETs are reduced. Simulations show that in addition to the maximum lattice temperature that is brought from ~ 694 K to ~ 366 K, DC and AC characteristics of the device have also improved drastically. The proposed transistor demonstrates lower negative differential resistance, more carrier mobility, higher saturation current, higher DC Transconductance, less delay time, and higher cut-off frequency compared to conventional silicon on insulator MOSFET. These promising properties and competitive advantages propose the designed device as a reliable alternative for conventional MOSFETs in high power and RF applications.

Self-Heating and Electrothermal Properties of Advanced Sub-5-nm Node Nanoplate FET

In this paper, Self-Heating Effect (SHE) of Gate-All-Around (GAA) nanoplate field effect transistor (FET) with variations of active area specifications including number of vertically stacked channels, metal gate thickness, and channel width, is investigated using TCAD simulations. Our research suggests that varying these architecture parameters not only affect overall performance of sub-5-nm node GAA nanoplate FET such as on-current degradation and time-delay, but also greatly impact thermal reliability such as lattice temperature and thermal resistance, which are comprehensively analyzed using the Figure of Merit ( FoM ). Furthermore, thermal reliability of GAA nanoplate-FET is analyzed from perspective of Hot Carrier Injection ( HCI )/Bias Temperature Instability ( BTI ) lifetime variation using maximum lattice temperature ( ${T}_{L,max}$ ) and metal gate thickness ( ${T}_{M}$ ).

Impact of Geometry, Doping, Temperature, and Boundary Conductivity on Thermal Characteristics of 14-nm Bulk and SOI FinFETs

In this paper, the self-heating effect (SHE) in 14-nm bulk and SOI FinFETs are investigated through the TCAD simulation. To achieve high authoritative evidences, the calibration is performed by ${I} _{\mathrm{ D}}$ - ${V} _{\mathrm{ G}}$ curve fitting based on the experimental data. The main contributions include: 1) The distribution of heat generation and temperature gradient along the channel are disclosed. Two peeks of heat generation are observed in source extension (SE) and drain extension (DE), respectively; 2) The dependence of maximum lattice temperature and thermal resistance on device geometry and parameters including fin width, fin height, length of SE and DE, the thickness of STI and BOX, doping concentration of extension, and gate voltage, are thoroughly analyzed; 3) The influence of SHEs on the electrical characteristic of FinFET under different ambient temperatures are also revealed. Moreover, the critical heat removal paths of bulk and SOI FinFETs are discussed. For the former, most of heat vertically diffuses to the substrate, and then to heat sink, whereas in SOI FinFET it firstly dissipates to source, drain, and gate, and then to heat sink. Finally, several optimization thumbs of SHEs are proposed.

Performance analysis of a novel trench SOI LDMOS with centrosymmetric double vertical field plates

Abstract A novel trench SOI LDMOS with centrosymmetric double vertical field plates structure (CDVFPT SOI LDMOS) is proposed in this paper. The 2-D device simulator MEDICI is used to investigate the characteristics of the proposed structure. Compared with the conventional trench SOI LDMOS (CT SOI LDMOS), the optimized device shows an obvious reduction in the specific on-resistance (Ron,sp) when its breakdown voltage (BV) is enhanced due to the introduction of centrosymmetric double vertical field plates structure. And when compared to previous device with floating vertical field plate trench SOI LDMOS (FVFPT SOI LDMOS), the overall performance of CDVFPT SOI LDMOS is also promoted. According to the simulation results, compared to a CT SOI LDMOS, the BV of CDVFPT SOI LDMOS increases from 188 V to 234 V. The Ron,sp, however, decreases from 2.30 mΩ·cm2 to 1.24 mΩ·cm2. In addition, the maximum lattice temperature at 1 mW/μm2 is slightly reduced.

Modeling of thermal runaway of carbonaceous materials: Graphite, biochar, and wood

Joule heating is an important mechanism in electronic devices. It must be carefully controlled to avoid the possibility of thermal runaway, which can happen in a fraction of a second. In contrast, there are some applications in which reaching high temperatures in such short times would be desired, such as in biomass gasification systems. In this paper, a transient one-dimensional model based on the energy equation coupled with the charge conservation and voltage equations is used to analyze thermal runaway for various carbonaceous materials ranging from wood, which is an electrical insulator, to biochar, which is a moderate electrical conductor, to graphite which has high electrical conductivity. Numerical results are obtained for the temporal evolution of the temperature and charge distribution, as well as, Joule heating, heat losses, electric field, and voltage. It is found that for higher applied voltages the charges accumulate mostly near the boundaries, and due to the increase of the electrical conductivity with temperature, the dynamics of thermal runaway are observed. In addition, a nondimensional analysis is performed to determine the operating conditions that generate significant Joule heating in relation to heat losses. The dimensionless time, Fo, to reach a prescribed maximum lattice temperature is calculated given a set of bias conditions and dimensions in the form of a nondimensional parameter M2.

Effect of carbon ion-beam irradiation on graphene oxide film

The effect of Carbon ion beam on graphene oxide film (GO) is investigated using X-ray diffraction, Raman microscopy and Fourier Transform Infra-red (FTIR) spectroscopy. It is shown that defects were created in GO and water molecules detached from GO layer as evident from X-ray diffraction, Raman microscopy and FTIR spectroscopy. Theoretical simulations were performed using different parameters and concluded that the maximum lattice temperature raised (574 K) by ion beam irradiation was below the annealing and melting temperature of GO.

A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

Thermionic cooling devices based on resonant-tunneling AlGaAs/GaAs heterostructure

We study by means of full quantum simulations the operating principle and performance of a semiconductor heterostructure refrigerator combining resonant tunneling filtering and thermionic emission. Our model takes into account the coupling between the electric and thermal currents by self-consistently solving the transport equations within the non-equilibrium Green’s function framework and the heat equation. We show that the device can achieve relatively high cooling power values, while in the considered implementation, the maximum lattice temperature drop is severely limited by the thermal conductivity of the constituting materials. In such an out-of-equilibrium structure, we then emphasize the significant deviation of the phonon temperature from its electronic counterpart which can vary over several hundred Kelvin. The interplay between those two temperatures and the impact on the electrochemical potential is also discussed. Finally, viable options toward an optimization of the device are proposed.

An improved SOI LDMOS with buried field plate

A silicon-on-insulator (SOI) lateral double-diffused MOSFET (LDMOSFET) with a buried field plate (BFP-LDMOS) is proposed. Its characteristics are studied using 2-D simulations. The proposed structure features double buried field plates which are surrounded by buried oxide (BOX) and connected to the source and drain electrode, respectively. The drain buried field plate (DBFP) prevents a premature breakdown at the interface of the silicon/BOX and enhances the dielectric field. The source buried field plate (SBFP) introduces a new electric-field peak and modulates the distribution of the horizontal electric field. In addition, the BFPs replace part of the BOX, which is useful to minimize self-heating effects (SHE). According to the simulation results, compared to a conventional SOI LDMOS (C-LDMOS), the breakdown voltage (BV) in the BFP-LDMOS increases from 128 V to 182 V. The specific on-state resistance (Ron,sp), however, decreases from 20.46 mΩ cm2 to 18.50 mΩ cm2. Moreover, the maximum lattice temperature at 1 mW/μm and Vgs = 10 V is reduced by 33.8 K compared to the C-LDMOS device.