Maximum Parallelism Research Articles

A 1000FPS@360,000pixels mixed-signal sensing with computing macro featuring analog compression and maximum parallelism for objective detection tasks

Ubiquitous vision sensors continuously collect data from the environment, imposing a significant processing burden. Especially, high-frame-rate convolution processing for large-scale pixel arrays presents substantial challenges. This paper proposes a mixed-signal sensing with computing macro featuring analog compression and maximum parallelism for high-frame-rate object detection tasks. A customized neural network (NN) architecture is designed specifically for object detection. Key circuitry modules, including signal readout, dark current offset, normalization, first-layer convolution, and pooling, are implemented in the analog domain, leading to high-quality information extraction and substantial data compression. Maximum parallelism in the first-layer convolution is realized in our proposed processing flow, ensuring high-frame-rate convolution for large-scale pixel arrays. Additionally, the subsequent NN layers are efficiently deployed on SRAM-based in-memory digital computing. The macro was designed using a 55-nm foundry process. Results show that our macro can achieve 1000 fps@360,000 pixels with a 63.8 TOPS throughput under 4/8-bit hybrid precision, outperforming the state-of-the-art in frame rate by 2–10 times.

Unidimensional community detection: A monte carlo simulation, grid search, and comparison.

Unidimensionality is fundamental to psychometrics. Despite the recent focus on dimensionality assessment in network psychometrics, unidimensionality assessment remains a challenge. Community detection algorithms are the most common approach to estimate dimensionality in networks. Many community detection algorithms maximize an objective criterion called modularity. A limitation of modularity is that it penalizes unidimensional structures in networks, favoring two or more communities (dimensions). In this study, this penalization is discussed and a solution is offered. Then, a Monte Carlo simulation using one- and two-factor models is performed. Key to the simulation was the condition of model error or the misfit of the population factor model to the generated data. Based on previous simulation studies, several community detection algorithms that have performed well with unidimensional structures (Leading Eigenvalue, Leiden, Louvain, and Walktrap) were compared. A grid search was performed on the tunable parameters of these algorithms to determine the optimal trade-off between unidimensional and bidimensional recovery. The best-performing parameters for each algorithm were then compared against each other as well as maximum likelihood factor analysis and parallel analysis (PA) with mean and 95th percentile eigenvalues. Overall, the Leiden and Louvain algorithms and PA methods were the most accurate methods to recover unidimensional and bidimensional structures and were the most robust to model error. More nuanced method recommendations for specific unidimensional and bidimensional conditions are provided. (PsycInfo Database Record (c) 2024 APA, all rights reserved).

Computational Modeling of Ganglion Cell Bicolor Opponent Receptive Fields and FPGA Adaptation for Parallel Arrays.

The biological system is not a perfect system, but it is a relatively complete system. It is difficult to realize the lower power consumption and high parallelism that characterize biological systems if lower-level information pathways are ignored. In this paper, we focus on the K, M and P pathways of visual signal processing from the retina to the lateral geniculate nucleus (LGN). We model the visual system at a fine-grained level to ensure efficient information transmission while minimizing energy use. We also implement a circuit-level distributed parallel computing model on FPGAs. The results show that we are able to transfer information with low energy consumption and high parallelism. The Artix-7 family of xc7a200tsbv484-1 FPGAs can reach a maximum frequency of 200 MHz and a maximum parallelism of 600, and a single receptive field model consumes only 0.142 W of power. This can be useful for building assistive vision systems for small and light devices.

OpenMP-based parallel MLPG solver for analysis of heat conduction

PurposeIn the present work, we focus on developing an in-house parallel meshless local Petrov-Galerkin (MLPG) code for the analysis of heat conduction in two-dimensional and three-dimensional regular as well as complex geometries.Design/methodology/approachThe parallel MLPG code has been implemented using open multi-processing (OpenMP) application programming interface (API) on the shared memory multicore CPU architecture. Numerical simulations have been performed to find the critical regions of the serial code, and an OpenMP-based parallel MLPG code is developed, considering the critical regions of the sequential code.FindingsBased on performance parameters such as speed-up and parallel efficiency, the credibility of the parallelization procedure has been established. Maximum speed-up and parallel efficiency are 10.94 and 0.92 for regular three-dimensional geometry (343,000 nodes). Results demonstrate the suitability of parallelization for larger nodes as parallel efficiency and speed-up are more for the larger nodes.Originality/valueFew attempts have been made in parallel implementation of the MLPG method for solving large-scale industrial problems. Although the literature suggests that message-passing interface (MPI) based parallel MLPG codes have been developed, the OpenMP model has rarely been touched. This work is an attempt at the development of OpenMP-based parallel MLPG code for the very first time.

A massive MPI parallel framework of smoothed particle hydrodynamics with optimized memory management for extreme mechanics problems

The dynamic failure process of structures under extreme loadings is very common in many fields of engineering and science. The smoothed particle hydrodynamics (SPH) method offers inherent benefits in dealing with complex interfaces and large material deformations in extreme mechanics problems. However, SPH simulations for 3D engineering applications are time-consuming. To address this issue, we introduce MPI (Message Passing Interface) in our SPH scheme to reduce computational time. Some optimizations are adopted to ensure the massive computation of the SPH method. In particular, an optimized memory management strategy is developed to control the memory footprint. With the present MPI-based massive parallelization of the SPH method, several validation examples are tested and analyzed. By comparing the present numerical results with the reference data, the dynamic failure process of complex structures subjected to extreme loadings like explosive and impact loadings can be well captured. A large number of particles, up to 2.04 billion, are adopted in the present simulations. The scaling tests show that the scalability of the massively parallel SPH program achieves a maximum parallel efficiency of 97% on 10020 CPU cores.

Computational performance of musculoskeletal simulation in OpenSim Moco using parallel computing.

Optimal control musculoskeletal simulation is a valuable approach for studying fundamental and clinical aspects of human movement. However, the high computational demand has long presented a substantial challenge, creating a need to improve simulation performance. The OpenSim Moco software package permits musculoskeletal simulation problems to be solved in parallel on multicore processors using the CasADi optimal control library, potentially reducing the computational demand. However, the computational performance of this framework has not been thoroughly examined. Thus, we aimed to investigate the computational speed-up obtained via multicore parallel computing relative to solving problems serially (i.e., using a single core) in optimal control simulations of human movement in OpenSim Moco. Simulations were solved using up to 18 cores with a variety of temporal mesh interval densities and using two different initial guess strategies. We examined a range of musculoskeletal models and movements that included two- and three-dimensional models, tracking and predictive simulations, and walking and reaching tasks. The maximum overall parallel speed-up was problem specific and ranged from 1.7 to 7.7 times faster than serial, with most of the speed-up achieved by about 6 processor cores. Parallel speed-up was generally greater on finer temporal meshes, while the initial guess strategy had minimal impact on speed-up. Considerable speed-up can be achieved for some optimal control simulation problems in OpenSim Moco by leveraging the multicore processors often available in modern computers. However, since improvements are problem specific, achieving optimal computational performance will require some degree of exploration by the end user.

Tissue P Systems With States in Cells

Tissue-like P systems with channel states are a type of classical membrane systems in which objects transferred among regions are controlled by states placed in the channels between regions. However, an important biological fact is the existence of a “barrier” to the diffusion of signal molecules, which tend to remain confined to some particular micro-habitat. This feature allows quorum sensing to convey information about the physiological state of spatially separated sub-populations. Therefore, in this article, we design a novel class-variant of P systems named <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tissue P systems with states in cells</i> (TSIC P systems). Here, each cell contains one and only one state at any moment (the environment has no state), and objects transferred among regions are controlled by states (or a state) that are placed in the corresponding cells (or a cell). We discuss the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">computability theory</i> of TSIC P systems by showing that Turing universality is acquired by TSIC P systems, which are worked both in a flat maximal parallelism and in a maximal parallelism. In addition, when cell division is considered in TSIC P systems, then tissue P systems with states in cells and cell division (TSICD P systems) are constructed. The (presumed) <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">computational efficiency</i> of TSICD P systems is reached by offering a uniform solution to the satisfiability problem.

Parallelising Control Flow in Dynamic-scheduling High-level Synthesis

Recently, there is a trend to use high-level synthesis (HLS) tools to generate dynamically scheduled hardware. The generated hardware is made up of components connected using handshake signals. These handshake signals schedule the components at runtime when inputs become available. Such approaches promise superior performance on “irregular” source programs, such as those whose control flow depends on input data. This is at the cost of additional area. Current dynamic scheduling techniques are well able to exploit parallelism among instructions within each basic block (BB) of the source program, but parallelism between BBs is under-explored, due to the complexity in runtime control flows and memory dependencies. Existing tools allow some of the operations of different BBs to overlap, but to simplify the analysis required at compile time they require the BBs to start in strict program order, thus limiting the achievable parallelism and overall performance. We formulate a general dependency model suitable for comparing the ability of different dynamic scheduling approaches to extract maximal parallelism at runtime. Using this model, we explore a variety of mechanisms for runtime scheduling, incorporating and generalising existing approaches. In particular, we precisely identify the restrictions in existing scheduling implementation and define possible optimisation solutions. We identify two particularly promising examples where the compile-time overhead is small and the area overhead is minimal and yet we are able to significantly speed up execution time: (1) parallelising consecutive independent loops; and (2) parallelising independent inner-loop instances in a nested loop as individual threads. Using benchmark sets from related works, we compare our proposed toolflow against a state-of-the-art dynamic-scheduling HLS tool called Dynamatic. Our results show that, on average, our toolflow yields a 4× speedup from (1) and a 2.9× speedup from (2), with a negligible area overhead. This increases to a 14.3× average speedup when combining (1) and (2).

Robust Data-Driven Sparse Estimation of Distribution Factors Considering PMU Data Quality and Renewable Energy Uncertainty - Part II: Scalability and Applications

This two-part paper proposes a data-driven, robust, and scalable sparse estimation framework of distribution factors (DFs). Part I proposes a novel Adaptive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> -Lasso estimator with theoretically guaranteed robustness. For solving this estimator, common algorithms are not scalable to large-scale systems since they often fail to converge under parallelism. This is addressed in Part II, where a novel Online Parallel Stochastic Coordinate Descent algorithm with theoretically guaranteed scalability is proposed. It can simultaneously update massive DF estimates by stochastic parallelism with fast convergence. It also works recursively under a multi-core setting and does not need step-size tuning, which is applicable for cloud-computing-based online parallel estimation. Convergence bounds of this algorithm are theoretically proven, and its speedup and maximum parallel core number are derived. These guide practical computational resource allocation for high efficiency. The benefits of the framework are showcased in real-time market operations under locational marginal pricing (LMP) and financial transmission right (FTR) mechanisms for congestion management. Thanks to its sparsity-promoting effect, robustness, and scalability, it allows for correctly and fast solving LMPs, congestion patterns, and FTR revenues against uncertainties. Test results on IEEE 300- and European 9241-bus systems via Alibaba Cloud validate the high scalability of this algorithm and benefits of the proposed framework to system applications.

P System with Fractional Reduction

Membrane computing is a branch of natural computing, which is a new computational model abstracted from the study of the function and structure of living biological cells. The study of numerical computation based on membrane computation has received increasing attention in recent years, where maximum parallelism in the execution of evolutionary rules plays an important role in improving the efficiency of numerical computation. Numbers in numerical computation are usually represented as decimals or fractions, and this paper investigates the fundamental problem in fraction representation and operations—fraction simplification. By improving the parallelization of two traditional fractional reduction algorithms, we design the corresponding fractional reduction class cells P System Π1 and P System Π2. Combining these two P Systems, this paper designs P System Π3. The feasibility and effectiveness of the P System designed in this paper are verified experimentally with the simulation software UPSimulator, and the characteristics and application scenarios of the three P Systems are analyzed.

An Interleaving Semantics of the Timed Concurrent Language for Argumentation to Model Debates and Dialogue Games

AbstractTime is a crucial factor in modelling dynamic behaviours of intelligent agents: activities have a determined temporal duration in a real-world environment, and previous actions influence agents’ behaviour. In this paper, we propose a language for modelling concurrent interaction between agents that also allows the specification of temporal intervals in which particular actions occur. Such a language exploits a timed version of Abstract Argumentation Frameworks to realise a shared memory used by the agents to communicate and reason on the acceptability of their beliefs with respect to a given time interval. An interleaving model on a single processor is used for basic computation steps, with maximum parallelism for time elapsing. Following this approach, only one of the enabled agents is executed at each moment. To demonstrate the capabilities of the language, we also show how it can be used to model interactions such as debates and dialogue games taking place between intelligent agents. Lastly, we present an implementation of the language that can be accessed via a web interface.

Timed concurrent language for argumentation with maximum parallelism

Abstract The timed concurrent language for argumentation (tcla) is a framework to model concurrent interactions between communicating agents that reason and take decisions through argumentation processes, also taking into account the temporal duration of the performed actions. Time is a crucial factor when dealing with dynamic environments in real-world applications, where agents must act in a coordinated fashion to reach their own goals. However, modelling complex interactions and concurrent processes may be challenging without the help of proper languages and tools. In this paper, we discuss the use of tcla for practical purposes and provide a working implementation of the language, endowed with a user interface available online, that serves the dual purpose of aiding the research in this field and facilitating the development of multi-agent systems based applications.

A parasitic-inertia piezoelectric actuator with isosceles trapezoidal flexible mechanism base on parasitic motion exploration and asymmetrical installation

Parasitic-inertia piezoelectric actuators have been widely studied for their ability to achieve both high positioning accuracy and large working strokes. However, backward motion results in parasitic-inertia piezoelectric actuators with the disadvantages of low efficiency and abrasion of driving foot. In this study, a parasitic-inertia piezoelectric actuator with an isosceles trapezoidal flexible mechanism is diegned and optimized to reduce backward motion considering the influence of parasitic motion proportion. It applies the asymmetrical installation of the piezoelectric stack to increase parasitic motion hence the reducing of backward motion. This study discusses the structure and working process of piezoelectric actuators and optimizes the design of flexible mechanism structure parameters with matrix displacement method and finite element method. A prototype of an parasitic-inertia piezoelectric actuator was manufactured, and a series of experiments were conducted. From the experiment, the piezoelectric actuator obtained a minimum backward motion percentage α = 18.36% and forward motion time percentage β = 95.9% at the frequency f = 1 Hz and the voltage U = 80 V. At U = 120 V, f = 500 Hz, the maximum motion speed of the actuator is 916 μm s−1; At U = 20 V and f = 1 Hz, the minimum positioning resolution of the actuator is 0.69 μm. At U = 120 V, f = 1 Hz, the maximum vertical load force is 1600 g, and the maximum parallel load force is 50 g. It has shown that the proposed isosceles trapezoidal flexible mechanism is feasible and can significantly reduce backward motion at the appropriate voltage. The mentioned characteristics of isosceles trapezoidal flexible mechanism can significantly alleviate the abrasion of driving foot, improve working efficiency. Also, it is vital for the miniaturization and practical application of parasitic-inertia piezoelectric actuators.

A Parameterized Parallel Design Approach to Efficient Mapping of CNNs onto FPGA

In recent years, Convolution Neural Networks (CNNs) have been widely applied to some artificial intelligence (AI) systems such as computer vision. Among many existing hardware accelerators, FPGA is regarded as a suitable platform for the implementation of CNNs because of its high energy efficiency and flexible reconfigurability. In this paper, a parameterized design approach is proposed to explore the maximum parallelism that could be possibly implemented in mapping a CNN algorithm onto targeted FPGA resources. Four types of parallelism are employed in our parameterized design to fully exploit the processing resources available in FPGA. Meanwhile, a hardware library consisting of a set of modules is established to accommodate various CNN models. Further, an algorithm is proposed to find the optimal level of parallelism dedicated to a constrained amount of resources. As a case study, the typical LeNet-5 is implemented on Xilinx Zynq7020. Compared with the existing works using the high-level synthesis design flow, our design obtains higher FPS and lower latency under the premise of using fewer LUTs and FFs.

Hybrid Delay‐Minimization Scheduling Algorithm of FT and MPTS in WSN Data Aggregation

The data acquisition of Internet of Things (IoT) is mostly brought out by wireless sensor networks (WSNs), and the efficiency of IoT is directly affected by the time delay in the process of data acquisition, which is researched mainly by the data aggregation of WSNs. Minimizing the delay in the data aggregation process is one of the most important operations. In order to reduce the data aggregation delay, a hybrid delay‐minimization data aggregation scheduling (HDDAS) algorithm is proposed, which optimizes the delay from the two main aspects that affect the delay, namely, the transmission path and the collision rate. Accordingly, the algorithm is divided into two phases: the aggregation tree construction and the data transmission scheduling. In the aggregation tree construction phase, the fat tree (FT) is introduced to generate an optimal aggregation tree with the shortest path; in the data transmission scheduling phase, the maximum parallel transmission set (MPTS) is adopted to increase the amount of the collision‐free data transmission. The simulation experiment results demonstrate that the HDDAS algorithm proposed in the paper has performed favorably in terms of the data aggregation delay.

Strategies to parallelize a finite element mesh truncation technique on multi-core and many-core architectures

Achieving maximum parallel performance on multi-core CPUs and many-core GPUs is a challenging task depending on multiple factors. These include, for example, the number and granularity of the computations or the use of the memories of the devices. In this paper, we assess those factors by evaluating and comparing different parallelizations of the same problem on a multiprocessor containing a CPU with 40 cores and four P100 GPUs with Pascal architecture. We use, as study case, the convolutional operation behind a non-standard finite element mesh truncation technique in the context of open region electromagnetic wave propagation problems. A total of six parallel algorithms implemented using OpenMP and CUDA have been used to carry out the comparison by leveraging the same levels of parallelism on both types of platforms. Three of the algorithms are presented for the first time in this paper, including a multi-GPU method, and two others are improved versions of algorithms previously developed by some of the authors. This paper presents a thorough experimental evaluation of the parallel algorithms on a radar cross-sectional prediction problem. Results show that performance obtained on the GPU clearly overcomes those obtained in the CPU, much more so if we use multiple GPUs to distribute both data and computations. Accelerations close to 30 have been obtained on the CPU, while with the multi-GPU version accelerations larger than 250 have been achieved.

RM-NTT: An RRAM-Based Compute-in-Memory Number Theoretic Transform Accelerator

As more cloud computing resources are used for machine learning training and inference processes, privacy-preserving techniques that protect data from revealing at the cloud platforms attract increasing interest. Homomorphic encryption (HE) is one of the most promising techniques that enable privacy-preserving machine learning because HE allows data to be evaluated under encrypted forms. However, deep neural network (DNN) implementations using HE are orders of magnitude slower than plaintext implementations. The use of very long polynomials and associated number theoretic transform (NTT) operations for polynomial multiplications is the main bottlenecks of HE implementation for practical uses. This article introduces RRAM number theoretic transform (RM-NTT): a resistive random access memory (RRAM)-based compute-in-memory (CIM) system to accelerate NTT and inverse NTT (INTT) operations. Instead of running fast Fourier transform (FFT)-like algorithms, RM-NTT uses a vector-matrix multiplication (VMM) approach to achieve maximal parallelism during NTT and INTT operations. To improve the efficiency, RM-NTT stores modified forms of the twiddle factors in the RRAM arrays to process NTT/INTT in the same RRAM array and employs a Montgomery reduction algorithm to convert the VMM results. The proposed optimization methods allow RM-NTT to significantly reduce NTT operation latency compared with other NTT accelerators, including both CIM and non-CIM-based designs. The effects of different RM-NTT design parameters and device nonidealities are also discussed.

GPS and InSAR derived evidences of intra‐basin stress and strike‐slip tectonics in the vicinity of 2001 (M7.7) earthquake, Kachchh, western India

The current geodetic investigation is based on nearly a decade of continuous Global Positioning System (GPS) data towards the western part of the Indian Plate (2009–2019). This research focused on the Kachchh Rift Basin (KRB), the seismically most active intra‐plate region of the Indian Plate, which has seen three ≥ M 7.0 earthquakes in the last two centuries. The GPS stations on the northern and southern margins show SSW and NNE directed motion, indicating that the KRB is currently under the influence of regional compressive stress on both flanks and the same is reflected in the form of earthquake activity in the center portion. Furthermore, the existence of intra‐basin stress, in addition to regional stress, increases strain accumulation and results in the creation of a Principal Deformation Zone (PDZ) in the central part of the KRB. The average annual deformation in the middle of KRB remains 1.0 ± 0.5 mm/year, while sites near the South Wagad Fault (SWF) experience 1.2 mm/year of fault parallel motion. The dominant fault normal motion along the flanks with a maximum fault parallel motion in the middle intimates the existence of strike‐slip tectonics in the central Kachchh. The geometric relationship of strike‐slip faults in a compressive margin and strain accumulation in pre‐existing faults (PDZ) is responsible for current strike‐slip and thrust motion in the Kachchh, including the 2001 Bhuj earthquake (M 7.7). Our geodetic model is well‐corroborated with the geological observations of the wrench fault model of strike‐slip faults. PS‐InSAR results in the northern part of the region between Khadir and Bela Islands show ≤6.0 mm of annual LOS displacement. GPS results indicate ≈ 1.3 to 1.4 ± 0.5 mm/year of fault parallel motion along the transverse Ekal Amrapar Fault (EAF). The non‐significant variation in GRACE‐derived TWS values (from 2009 to 2018) rules out non‐tectonic deformation in the vicinity of EAF and thus points to tectonic activity as the cause of the derived deformation in the region.

Towards Optimal Parallelism-Aware Service Chaining and Embedding

Emerging 5G technologies can significantly reduce end-to-end service latency for applications requiring strict quality of service (QoS). With network function virtualization (NFV), to complete a client’s request from those applications, the client’s data can sequentially go through multiple service functions (SFs) for processing/analysis but introduce additional processing delay. To reduce the processing delay from the serially-running SFs, network function parallelism (NFP) that allows multiple SFs to run in parallel is introduced. In this work, we study how to apply NFP into the SF chaining and embedding process such that the latency, including processing and propagation delays, can be jointly minimized. We introduce a novel augmented graph to address the parallel relationship constraint among the required SFs. Considering parallel relationship constraints, we propose a novel problem called parallelism-aware service function chaining and embedding (PSFCE). For this problem, we propose a near-optimal maximum parallel block gain (MPBG) first optimization algorithm when computing resources at each physical node are enough to host the required SFs. When computing resources are limited, we propose a logarithm-approximate algorithm, called parallelism-aware SFs deployment (PSFD), to jointly optimize processing and propagation delays. We conduct extensive simulations on multiple network scenarios to evaluate the performances of our schemes. Accordingly, we find that (i) MPBG is near-optimal, (ii) the optimization of end-to-end service latency largely depends on the processing delay in small networks and is impacted more by the propagation delay in large networks, and (iii) PSFD outperforms the schemes directly extended from existing works regarding end-to-end latency.

HIPA: A hybrid load balancing method in SSDs for improved parallelism performance

NAND Flash-based SSDs have been widely adopted as underlying storage devices in storage systems thanks to high random performance in the SSDs. Because of inherent rich parallelism resources (channel, chip, plane, and die) inside an SSD, many researchers pay much attention on parallelism improvement. Page allocation policies (static and dynamic page allocation) in an SSD aim to translate logical addresses of I/O requests on the host into physical addresses in flash memory space. Existing static page allocation policies suffer from severe load unbalance inside SSDs. Dynamic allocation policies employed in high-performance SSDs address the load balancing issue. However, dynamic allocation-based I/O requests flow into fewer parallelism resources, deteriorating read I/O-requests parallelism. Recognizing that SSD performance can be optimized by reducing read parallelism loss, we propose a hybrid page allocation strategy named HIPA to fully exploit the advantages of dynamic and static allocation to achieve read/write parallelisms inside an SSD. HIPA embraces a load prediction mechanism to monitor die-level load in real-time, thereby determining a page allocation policy based on the status of die-level load. A static page allocation policy is triggered in case of balanced die-level load. When performance degrades due to imbalance in die-level load, HIPA dynamically changes the gear to a dynamic allocation policy, aiming to balance the load on dies. Thus, HIPA achieves the maximum read parallelism rather than crumbling write performance. Conducting the extensive experiments, we validate the advantages of HIPA in terms of average response time, plane-level write, and erase standard deviation. The findings unveil that compared with the four popular page allocation policies (CWDP, CHIP-D, DIE-D, and PLANE-D), HIPA slashes the average response time by up to 58% with an average of 20% and 81% with an average of 33% compared with the dynamic allocation (DIE-D) with the lowest response time and the static strategy, respectively; (2) drives up the write standard deviation degree of the static strategy by up to 44%; (3) improves erase standard deviation rate by up to 43%.