Matching Inductor Research Articles

Comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process

AbstractThis paper presents a comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers (PAs) designed for 35–42 GHz millimeter‐wave applications, utilizing a 130 nm CMOS process. The proposed RF PAs are well suited for wide frequency‐band millimeter‐wave and 5G radio transmitters. A comprehensive study of limiting factors in amplifier efficiency is presented in this paper. The study encompasses an analysis of all the factors that restrict the efficiency of the switched power amplifier. The first proposed power amplifier is based on the Class E/F2 architecture, comprising a parallel capacitor, second harmonic resonance circuit, and output matching network. Conversely, the second suggested power amplifier is constructed using the inverse Class‐‐F topology, which includes harmonic termination and matching networks. The harmonic termination circuit incorporates a second harmonic resonance network and utilizes a parasitic capacitor to control the harmonic components. Both the proposed Class E/F2 and inverse Class‐‐F architectures are employed to reshape the drain current and voltage waveforms, aiming to reduce the overlap between them and, consequently, improve efficiency. The suggested power amplifiers comprise a driver Class‐‐AB stage and a power stage constructed based on either the Class E/F2 architecture or inverse Class‐‐F topology, utilizing harmonic termination networks at the output load. Two new designs of high‐Q factor on‐chip finger capacitors have been implemented to improve efficiency and radio frequency performance. Achieving input matching and inter‐stage matching is facilitated by employing two novel on‐chip transformers designed for maximum power transfer. Additionally, an inter‐stage matching inductor is utilized in a cascode configuration to enhance the overall RF performance. The on‐chip transformers, inductors, and finger capacitors are designed using the HFSS software program. S‐parameter files (SNP files) of the designed on‐chip components are extracted and inserted into the simulation tool to ensure accurate results. The proposed Class E/F2 power amplifier achieves a constant power of 14.9 dBm, an extreme power added efficiency (PAE) of 11.7%, and a maximum gain of 13.74 dB. In contrast, the suggested inverse Class‐‐F power amplifier attains a constant power of 15.4 dBm, a peak PAE of 12.6%, and a maximum gain of 14.8 dB. The DC power consumption is 73 and 66 mW for the proposed Class E/F2 and inverse Class‐‐F PAs, respectively, while their active sizes are 0.14 and 0.2 mm2.

Design for SAW Antenna-Plexers with Improved Matching Inductance Circuits.

This study designs antenna-plexers, including a surface acoustic wave (SAW) extractor and an upper- and mid-high band (UHB + MHB) diplexer, for LTE 4G and 5G bands using carrier aggregation. The SAW extractor combines a bandpass filter (BPF) and a band-stop filter (BSF) in a single unit that consists of eight modified Butterworth-van Dyke (mBVD) resonators that resonate in parallel with an inductor and SAW resonators. This BSF behaves as a high-pass filter at frequencies lower than the designed WIFI band and as a capacitor at higher frequencies. The SAW extractor meets product specifications in the frequency range 0.7 to 2.7 GHz. The UHB + MHB diplexer, which is composed of a microwave filter, a SAW filter, and a simple matching inductor, uses frequency response methods to create an RF component for 2.4 GHz + WIFI 6E applications. The design uses a SAW's interdigital transducer (IDT) structure, and the experimental results are in agreement with the simulation results, so the design is feasible.

An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3

In this article, an ultra-low-voltage 2.4-GHz radio frequency (RF) receiver front-end architecture targeting the removal of output flicker noise is presented, making it possible to use zero-IF topology for narrow-band communication standards. The trans-impedance amplifier (TIA) is built on the proposed hybrid operational trans-conductance amplifier (OTA) with a switched-capacitor (SC) amplifier as the first gain stage and an active primary–secondary amplifier as the second gain stage, achieving an imperceptible flicker-noise corner frequency. With the SC gain stage, the interstage common-mode voltage can be set to 0 V, which reduces the minimum supply voltage to 0.5 V. As another benefit, dc offset compensation (DCOC) is performed inherently in the interstage sampling and coupling process. Fabricated in 28-nm RF CMOS process, the front-end prototype, including an on-chip matching inductor, occupies a die area of 0.8 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . Operating in the Industrial Scientific Medical (ISM) frequency band of 2.4 GHz with 1-MHz IF bandwidth, the front end provides a 36–40-dB conversion gain, an 11.5-dBm OIP3, and a flicker-noise corner frequency less than 10 kHz with the supply voltage ranging from 0.5 to 0.6 V. The RF impedance matching network provides passive voltage gain before the low-noise trans-conductance amplifier (LNTA), achieving a 4.5-dB noise figure (NF) with 0.8-mA biasing current in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_m$</tex-math> </inline-formula> stage. With the ultra-low supply voltage and the passive IF gain stage, the power consumption of the proposed front end is only 610 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> W under a 0.53-V supply voltage.

DC-10 GHz broadband linear power amplifier for 5G applications using 180 nm CMOS technology

This article suggests a broadband linear power amplifier (PA) for DC-10 GHz for Fifth-generation (5G) and multi-standard applications using 180 nm CMOS technology. The suggested radio frequency power amplifier is appropriate for wideband LTE, IoT, WSN, multi-standard, and 5G radio frequency transmitters. T-coil peaking and bridged-shunt-series peaking amplifiers are used for bandwidth extension and gain flatness. Also, the interstage matching inductors between common source and common gate transistors are applied to improve radio frequency achievement. The suggested PA consists of four stages as follows; input stage, two stages using the T-coil peaking technique, and the last stage utilizing bridged-shunt-series peaking topology. The input stage is a complementary current reuse (CCR) common gate with active shunt feedback (SFB) architecture. It is utilized to extend the matching of RF input impedance with agreeable linearity and power gain at little power consumption. The second stage works in class-C operation to enhance the efficiency and reduce DC power consumed whereas the class-AB mode is utilized in the third and fourth stages to improve the output power. The suggested PA obtains a peak constant power equal to 14.25 dBm, a maximum Power-Added-Efficiency (PAE) of 16 %, and a peak gain equal to 22 dB. The proposed power amplifier dissipates a DC power of 80 mW. The die size of the proposed power amplifier equals 1mm2, whereas the total chip size includes the pads is 1.62mm2.

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

AbstractHigh‐efficiency and high‐linearity three‐stage transformer‐coupled power amplifier (PA) and power combiner for millimeter‐wave applications using 130 nm CMOS technology are presented in the paper. The suggested PA uses transformer coupled for input, inter‐stage, and output matching networks where the inter‐stage matching inductors are utilized to enhance the RF performance. The proposed power amplifier is composed of three stages: first, driver, and power stages. The first stage operates in a class‐C to improve the efficiency and decrease power dissipated while a class‐AB is used in the driver and power stages to maximize the output power. The proposed PA and power combiner designs are suitable for mm‐wave 5G applications. The coupling transformers, inter‐stage matching inductors, and output combiner are analyzed and designed using Ansoft high‐frequency structure simulator (HFSS) and achieve high‐quality factor and high‐coupling coefficient over the frequency range from 26 to 33 GHz. The proposed three‐stage transformer‐coupled power amplifier covers a frequency band from 26 GHz to 33 GHz with a saturated output power of 13.1 dBm, a peak power added efficiency (PAE) equals 19.1%, and a maximum power gain of 13.25 dB. Whereas the proposed power combiner has a saturated output power of 16.3 dBm, a maximum PAE equals 20.5% and a peak gain of 16.5 dB. The proposed three‐stage transformer‐coupled PA and power combiner consume low power of 65 mW and 128 mW, respectively. Moreover, the adjacent channel power ratios (ACPR) of the proposed PA and power combiner equal −30 dBc and −36 dBc, respectively, for 20 MHz channel bandwidth. Finally, the active areas of the proposed power amplifier and power combiner equal 0.25 mm2 and 0.69 mm2, respectively, while the chip areas are 0.55 mm2 and 1 mm2, respectively.

Design for Acoustic Wave Multiplexers With Single Inductor Matching Network Using Frequency Response Fitting Method

This study proposes a new acoustic wave (AW) multiplexer topology with a single-inductor matching network for carrier aggregation (CA) in the fifth-generation communication systems. To satisfy the desired specifications of all the multiplexer ports based on ladder-type filters, the frequency response fitting method (FRFM) is proposed to obtain the BVD parameters for each AW resonator. Using the proposed computer-aided method, a parameter solution can be obtained under practical design limitations, such as the selection of the piezoelectric material, properties of the manufacturing process, and used circuit topology. Furthermore, a measurement of a band 1 and 3 surface acoustic wave (SAW) multiplexer is set up to confirm the feasibility of the proposed FRFM. The designed SAW multiplexer based on the lithium tantalate with Euler angle (0, -38, 0), 42&#x00B0;YX-LiTaO3, is arranged. The designed quadplexer achieves high selectively with a return loss (RL), stopband reflection, and isolation better than -12 dB, -43 dB, and -50 dB, respectively, in a 2.15 &#x00D7; 2.65 mm² occupation. The measurement results confirm the feasibility of the multiplexer topology and the proposed FRFM. The approach is also extended to a quadplexer design with band 4 and 25 and a hexaplexer design with band 1, 3, and 7 for CA applications, demonstrating its flexibility and simplicity.

A Low-Noise, High-Gain, and Small-Size UWB Mixer Utilizing Negative Impedance Technique and Source Input Method

This paper presents an ultra-wideband (UWB) down-conversion mixer with low-noise, high-gain and small-size. The negative impedance technique and source input method are applied for the proposed mixer. The negative impedance achieves the dynamic current injection and increases the mixer output impedance, which reduces the mixer flicker noise and increases its conversion gain. The source input method allows the input matching networks to be cancelled, avoiding the noise and loss introduced by the matching resistors, saving the chip area occupied by the matching inductors. The proposed mixer is designed in 45-nm SOI process provided by GlobalFoundries. The simulation results show a conversion gain of 11.4–14.3 dB, ranging from 3.1 to 10.6 GHz, a minimum noise figure of 9.8 dB, a RF port return loss of less than −11 dB, a port-to-port isolation of better than −48 dB, and a core chip area of 0.16 × 0.16 mm2. The power consumption from a 1 V supply voltage is 2.85 mW.

A miniaturized 35 GHz 65‐nm CMOS digital‐controlled differential variable gain amplifier

AbstractThis paper presents a 35 GHz differential variable gain amplifier (VGA) with 4‐bit digital‐controlled gain‐tuning using 65‐nm CMOS process. Using the proposed miniaturized differential matching inductors, a core size of the VGA is only 0.53 0.26 mm. The digital gain control mechanism is achieved using the digital version current steering topology. The measured gain control range of the VGA is from 17.4 to 9 dB at 35 GHz with 16 different linear‐in‐dB gain states. Thus, this work achieves the maximum peak gain per unit core size and maintains a much better gain control range per unit core size. The measured root mean square gain error is &lt;0.29 dB and phase error is &lt; from 34 to 36.5 GHz.

Analysis of impedance matching for a spherical multi-degree-of-freedom ultrasonic motor.

A novel spherical multi-degree-of-freedom ultrasonic motor is designed, which can achieve three-degree-of-freedom motion through the cooperative drive of three built-in traveling wave stators. The novel ultrasonic motor has the characteristics of compact structure and high power density. Additionally, in order to solve the problem of impedance mismatch between the ultrasonic motor and the driving power supply, a semi-analytical method of impedance matching based on parallel resonance is proposed according to the impedance characteristics of ultrasonic motor. Through the combination of theoretical derivation and finite element simulation, the ultrasonic motor impedance matching on the impedance circle is analyzed. By this method, the optimum matching inductor of the motor is determined. After matching, the motor obtains a larger vibration amplitude and higher transmission efficiency. Finally, the reliability of the method is verified by simulation and experiment, which provides a reference for further improving the motor performance.

58 GHz CMOS VCO with 16% efficiency

This Letter presents a millimetre-wave CMOS oscillator, which achieves 4.9 dBm output power with 16% peak power efficiency. A phase noise of − 98 dBc / Hz at 1 MHz offset frequency and 26.7% tuning range around 57.5 GHz centre frequency were verified experimentally. To the best knowledge of the authors, the output power, efficiency, and phase noise performance are the best among fundamental CMOS oscillators in the frequency range of interest, while the tuning range is the third highest result reported to date. The circuit occupies a silicon area of ∼ 9000 μ m 2 without the matching inductors on a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology.

A 22-to-47 GHz 2-Stage LNA With 22.2 dB Peak Gain by Using Coupled L-Type Interstage Matching Inductors

This article presents a 22–47 GHz wideband low-noise amplifier (LNA) with coupled L-type interstage matching inductors. The coupled inductors extend the bandwidth of LNA by moving zeros to lower frequencies to cancel the effect of poles. Meanwhile, asymmetric L-type inductors with different inductances can be designed separately to achieve better gain flatness. In addition, the quality factor of coupled inductors is also slightly improved without significantly changing their inductance. The LNA is fabricated in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, and it occupies a core area of 0.13 mm2. The LNA achieves a peak gain of 22.2 dB with the 3dB bandwidth of 22–47 GHz (fractional bandwidth up to 72.5%). The measured NF varies between 3.0 and 4.3 dB from 22 to 47 GHz. The measured input 1-dB gain compression point is stable from −23.9 to −22.6 dBm in the entire 3-dB gain bandwidth. The chip consumes a total power of 9.5 mW from a 1.2 V supply.

120-GHz 8-Stage Broadband Amplifier With Quantitative Stagger Tuning Technique

A novel quantitative design method is proposed herein for a 120-GHz 8-stage broadband amplifier using the stagger tuning technique. The pole frequencies of the unit amplifiers are determined by the parasitic capacitors and the size of the matching inductors, and resonance peaks are formed at the pole frequency. We proposed the stagger tuning technique at two different frequencies, where an inductance of four stages is chosen to match the pole frequency at a lower frequency (fL) and an inductance of the other four stages is chosen for the upper frequency (fH). With this technique, the maximum bandwidth can be achieved with the given amplifier gain. Moreover, it was shown that the amplifier designed with stagger tuning at two different frequencies yielded the lowest noise figure in the target band because the gain was concentrated in the target band. A 120-GHz 8-stage amplifier is designed with the proposed technique and fabricated using 40-nm CMOS technology. The measured peak gain of the amplifier is 20.6 dB, and the 3-dB bandwidth is 40.6 GHz while consuming 45-mW of dc power.

$\pi$ -SCR Device for Broadband ESD Protection in Low-Voltage CMOS Technology

Electrostatic discharge (ESD) protection design is needed for integrated circuits; however, the ESD protection devices near the I/O pad may cause negative impacts on the high-frequency performance. To achieve both excellent ESD robustness and good broadband performance, a silicon-controlled rectifier (SCR) with trigger diodes, a matching inductor, and a reversed diode to form a novel $\pi $ -SCR device is presented in this brief. As compared with the conventional $\pi $ -diode in silicon, the $\pi $ -SCR can reduce the clamping voltage during the critical positive-to- $V_{\text {SS}}$ (PS) ESD test, and the high-frequency performance is not seriously degraded (insertion loss $\pi $ -SCR device does not suffer the latch-up issue in low-voltage CMOS technology, and it has the potential to further reduce the clamping voltage during other ESD tests. Therefore, the novel $\pi $ -SCR device will be a good choice for broadband ESD protection in low-voltage CMOS technology.

Millimeter wave balun design and optimization based on compensation matching capacitors and active S parameter

AbstractA balun design algorithm based on the compensation matching capacitors and the active S parameter is given in this paper. Compared with the inductor matching network, the compensation matching capacitors not only compensate the phase and the amplitude error of the balun, but also occupy a compact chip area. Considering the coupling between two differential terminals of the balun, the active S parameter is adopted. On the basis of the active S parameter, the reflection coefficients of two differential terminals are calculated directly. On the basis of this algorithm, the simulated phase error and the amplitude error of the balun are less than 0.97° and 0.13 dB, from 15 to 18 GHz. Moreover, a 5‐bit differential switch‐type phase shifter with two baluns is designed in the 180‐nm complementary metal oxide semiconductor (CMOS) process at Ku band. Thanks to the small phase error of two baluns, the tested RMS phase error is less than 4°, from 15 to 18 GHz.

Frequency changing technique for efficient fast start-up RF energy harvesting

PurposeThe purpose of the paper is to present a frequency-changing technique to realize a fast start-up radio frequency (RF) energy harvester.Design/methodology/ApproachFirst, a simple analysis of the input impedance of the rectifier circuit is presented, and based on the analysis, it is shown how the input impedance of the rectifier is changed during the rectifier charging. Then, the frequency-changing technique is presented in which the variation of the rectifier input reactance (capacitance) is partly compensated by changing the frequency of the transmitted RF signal. A harvester consisting of a four-stage rectifier and a simple series matching inductor, implemented based on Schottky diode, is employed to verify the technique.FindingsWith the input available power of −12 dBm, the simulated and the measured results prove that the proposed frequency-changing method compared to the typical fixed-frequency method shows more than 30 per cent decrease in the transient time to reach 0.5 V output voltage, while the final harvested output voltage is unchanged.Originality/ValueA frequency-changing technique is presented.

Low-Cost, Direct-Fed Slot Antenna Built in Metal Cover of Notebook Computer for 2.4-/5.2-/5.8-GHz WLAN Operation

The slot antenna has been utilized for some recent notebook computers on the market. The FR4 substrates are usually required to print the metal patterns for coupled-feeding the 2.4 GHz (2400–2484 MHz) slot and also for contributing the 5.2 GHz (5150–5350 MHz) and 5.8 GHz (5725–5825 MHz) bands. This communication presents a simple, direct-fed slot antenna with a low profile of 7 mm to the top edge of the metal cover for 2.4-/5.2-/5.8-GHz WLAN operation. The antenna design did not require any substrate and can be implemented directly in the metal cover of a notebook computer at low cost. The design comprised two parallel-connected, 0.5-wavelength-slot portions, formed in a linear structure of length 79 mm and constant width 2 mm, and fed by a common antenna feed port using a mini-coaxial cable. The larger slot generated a 0.5-wavelength resonant mode in the 2.4-GHz band and a 1-wavelength mode for 5.2-GHz operation. The smaller slot operated in a 0.5-wavelength resonant mode, which covered the 5.8-GHz band. With a matching inductor properly set in the slot, good input impedance over the 2.4-, 5.2-, and 5.8-GHz bands can be attained.

Effect of the Matching Circuit on the Electromechanical Characteristics of Sandwiched Piezoelectric Transducers.

The input electrical impedance behaves as a capacitive when a piezoelectric transducer is excited near its resonance frequency. In order to increase the energy transmission efficiency, a series or parallel inductor should be used to compensate the capacitive impedance of the piezoelectric transducer. In this paper, the effect of the series matching inductor on the electromechanical characteristics of the piezoelectric transducer is analyzed. The dependency of the resonance/anti-resonance frequency, the effective electromechanical coupling coefficient, the electrical quality factor and the electro-acoustical efficiency on the matching inductor is obtained. It is shown that apart from compensating the capacitive impedance of the piezoelectric transducer, the series matching inductor can also change the electromechanical characteristics of the piezoelectric transducer. When series matching inductor is increased, the resonance frequency is decreased and the anti-resonance unchanged; the effective electromechanical coupling coefficient is increased. For the electrical quality factor and the electroacoustic efficiency, the dependency on the matching inductor is different when the transducer is operated at the resonance and the anti-resonance frequency. The electromechanical characteristics of the piezoelectric transducer with series matching inductor are measured. It is shown that the theoretically predicted relationship between the electromechanical characteristics and the series matching inductor is in good agreement with the experimental results.

Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency) CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to reduce parasitic capacitance at the band of 24 GHz. The proposed sensor has low cost and low power dissipation since it is realized using CMOS process. The proposed sensor showed the lowest noise figure of 2.9 dB and the highest conversion gain of 40.2 dB as compared to recently reported research results. It also showed small chip size of 0.56 mm2, low power dissipation of 39.5 mW, and wide operating temperature range of −40 to +125°C.

High-Gain and Low-Power Power Amplifier for 24-GHz Automotive Radars

This paper presents a high gain and low power 24-GHz power amplifier (PA) for the short range automotive radar. The proposed circuit is implemented using TSMC 0.13-µm RF CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5-V supply. To improve power gain of the amplifier, it has a 2-stage cascode scheme. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF (radio frequency) are used to reduce parasitic capacitances at the band of 24 GHz. The proposed RF amplifier has low cost and low power dissipation since it is realized using all CMOS processes. The proposed circuit showed the smallest chip size of 0.12 mm 2 , the lowest power dissipation of 44.3 mW and the highest power gain of 24.04 dB as compared to recently reported research results.

Highly linear low voltage low power CMOS LNA

A highly linear, low voltage, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP3 is improved by 12dB in contrast to the conventional folded cascode LNA, reaching −1dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S21) of 12.25dB with a noise figure of 3.5dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V.