Massive Parallel Systems Research Articles

Hamiltonian cycles of balanced hypercube with disjoint faulty edges

The balanced hypercube BHn, a variant of the hypercube, is a novel interconnection network topology for massive parallel systems. It is showed in [Theor. Comput. Sci. 947 (2023) 113708] that for any edge subset F of BHn there exists a fault-free Hamiltonian cycle in BHn−F for n≥2 with |F|≤5n−7 if the degree of every vertex in BHn−F is at least two and there exist no f4-cycles in BHn−F. In this paper, we consider the existence of Hamiltonian cycles of BHn when F is a matching (a set of disjoint edges), and show that each edge e∉F lies on a fault-free Hamiltonian cycle of BHn−F with n≥2. The number of faulty edges in F can be up to 22n−1, which is exponential to the dimension n.

Hamiltonian cycles of balanced hypercube with more faulty edges

The balanced hypercube BHn, a variant of the hypercube, is a novel interconnection network for massive parallel systems. It is known that the balanced hypercube remains Hamiltonian after deleting at most 4n−5 faulty edges if each vertex is incident with at least two edges in the resulting graph for all n≥2. In this paper, we show that there still exists a Hamiltonian cycle in BHn for n≥2 after deleting a set F of edges with |F|≤5n−7 if the degree of every vertex in BHn−F is at least two and there exists no f4-cycles in BHn−F, which improves some known results.

Avoided mode-crossing assisted single soliton formation

Single soliton micro-comb (SMC) provides a tool for nonlinear optics investigation, and has become a novel integrated coherent source for portable optical clock, precise measurement and massive parallel optical communication systems, etc. Here, we demonstrate a new approach for deterministic single soliton generation in a microresonator. The microresonator is pumped at a mode with a frequency shift of −160 MHz due to the avoided mode-crossing (AMX), which enhances the local dispersion to form native mode spaced (NMS) Turing pattern directly. The Turing pattern provides a potential field to capture and sustain single soliton. Moreover, the high power chaotic microcomb is absent, which enables stable accessing of single SMC state. Our experiment presents a different dynamics of single soliton generation, which paves a new way for stable and deterministic single soliton micro-comb formation for practical applications.

Calculating the Moore–Penrose Generalized Inverse on Massively Parallel Systems

In this work, we consider the problem of calculating the generalized Moore–Penrose inverse, which is essential in many applications of graph theory. We propose an algorithm for the massively parallel systems based on the recursive algorithm for the generalized Moore–Penrose inverse, the generalized Cholesky factorization, and Strassen’s matrix inversion algorithm. Computational experiments with our new algorithm based on a parallel computing architecture known as the Compute Unified Device Architecture (CUDA) on a graphic processing unit (GPU) show the significant advantages of using GPU for large matrices (with millions of elements) in comparison with the CPU implementation from the OpenCV library (Intel, Santa Clara, CA, USA).

Reliability of arrangement networks in terms of the h-restricted edge connectivity

The h-restricted edge connectivity λh is an important parameter to measure the reliability of massive parallel computing system. The λh of G is the minimum cardinality of a set of edges in G, if any, whose deletion disconnects G, and every remaining component has minimum degree at least h. The arrangement graph is a generalization of the star graph, but its order is more flexible than that of the star graph. This paper investigates the h-restricted edge connectivity of the (n,k)-arrangement graph An,k, and determines that λ1(An,k)=2k(n−k)−2, λ2(An,k)=3k(n−k)−6 with k≤n−2.

A 3D graphics rendering pipeline implementation based on the openCL massively parallel processing

Recently, massively-parallel computing libraries and devices are much widely used, in addition to the traditional 3D graphics systems. In this paper, we present a full 3D fixed-function graphics pipeline, based on the OpenCL, which is one of the most widely used massively-parallel computing library. The full 3D graphics features including WebGL, Web3D and others can be implemented on the massively-parallel computations, without underlying 3D graphics hardware support. Many previous works focused on another massively-parallel system of CUDA, which has a drawback of limited availability. In contrast, we designed and implemented a new architecture with OpenCL, which is now available on various computing devices, including most CPUs, GPUs, and at least theoretically, special-purpose embedded FPGAs. Our work provides full 3D graphics features on OpenCL-capable systems, without dedicated 3D graphics hardware, to finally make 3D graphics features ubiquitous. Technically, we used a top-down approach in its rendering, from the whole screen to precise pixels. At each stage, we tuned our OpenCL implementations and also their global and local parameter spaces. We present the details of our design and also the final result of our implementation, and show its correctness and efficiency.

SpiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System

SpiNNaker is a massively-parallel computer system optimized for the simulation, in real time, of very large networks of spiking neurons. The system consists of over 1 million, energy-efficient ARM cores distributed over 57,600 SpiNNaker chips, each of which contains 18 cores interconnected by a neurobiologically-inspired, asynchronous (clock-less) Network-on-Chip. The NoC is extended to the chip boundary for chip-to-chip communication. To construct the massively-parallel system, SpiNNaker boards, housing 48 SpiNNaker chips, are connected together using FPGA-based, high-speed serial links. This paper presents some of the novel aspects of the design and implementation of the bespoke interconnect, including a credit-based, reliable frame transport protocol that allows the multiplexing of asynchronous SpiNNaker channels over the serial links, and an efficient FPGA-to-SpiNNaker chip interface that provides twice the throughput of traditional asynchronous interfaces. SpiNNaker houses 3,600 Xilinx Spartan-6 FPGAs, provides a bisection bandwidth of 480 Gbit/s, and ran the first-ever, true real-time brain cortical simulation [1] - a feat not currently achievable using conventional HPCs or GPUs.

Stochastic optimization of GeantV code by use of genetic algorithms

GeantV is a complex system based on the interaction of different modules needed for detector simulation, which include transport of particles in fields, physics models simulating their interactions with matter and a geometrical modeler library for describing the detector and locating the particles and computing the path length to the current volume boundary. The GeantV project is recasting the classical simulation approach to get maximum benefit from SIMD/MIMD computational architectures and highly massive parallel systems. This involves finding the appropriate balance between several aspects influencing computational performance (floating-point performance, usage of off-chip memory bandwidth, specification of cache hierarchy, etc.) and handling a large number of program parameters that have to be optimized to achieve the best simulation throughput. This optimization task can be treated as a black-box optimization problem, which requires searching the optimum set of parameters using only point-wise function evaluations. The goal of this study is to provide a mechanism for optimizing complex systems (high energy physics particle transport simulations) with the help of genetic algorithms and evolution strategies as tuning procedures for massive parallel simulations. One of the described approaches is based on introducing a specific multivariate analysis operator that could be used in case of resource expensive or time consuming evaluations of fitness functions, in order to speed-up the convergence of the black-box optimization problem.

A parallel finite volume scheme preserving positivity for diffusion equation on distorted meshes

Parallel domain decomposition methods are natural and efficient for solving the implicity schemes of diffusion equations on massive parallel computer systems. A finite volume scheme preserving positivity is essential for getting accurate numerical solutions of diffusion equations and ensuring the numerical solutions with physical meaning. We call their combination as a parallel finite volume scheme preserving positivity, and construct such a scheme for diffusion equation on distorted meshes. The basic procedure of constructing the parallel finite volume scheme is based on the domain decomposition method with the prediction‐correction technique at the interface of subdomains: First, we predict the values on each inner interface of subdomains partitioned by the domain decomposition. Second, we compute the values in each subdomain using a finite volume scheme preserving positivity. Third, we correct the values on each inner interface using the finite volume scheme preserving positivity. The resulting scheme has intrinsic parallelism, and needs only local communication among neighboring processors. Numerical results are presented to show the performance of our schemes, such as accuracy, stability, positivity, and parallel speedup.© 2017 Wiley Periodicals, Inc. Numer Methods Partial Differential Eq 33: 2159–2178, 2017

Scalable Single Source Shortest Path Algorithms for Massively Parallel Systems

We consider the single-source shortest path (SSSP) problem: given an undirected graph with integer edge weights and a source vertex $v$ , find the shortest paths from $v$ to all other vertices. In this paper, we introduce a novel parallel algorithm, derived from the Bellman-Ford and Delta-stepping algorithms. We employ various pruning techniques, such as edge classification and direction-optimization, to dramatically reduce inter-node communication traffic, and we propose load balancing strategies to handle higher-degree vertices. These techniques are particularly effective on power-law graphs, as demonstrated by our extensive performance analysis. In the largest tested configuration, an R-MAT graph with $2^{38}$ vertices and $2^{42}$ edges on 32,768 Blue Gene/Q nodes, we have achieved a processing rate of three Trillion Edges Per Second (TTEPS), a four orders of magnitude improvement over the best published results.

Forest Fire Danger Assessment Using SPMD-Model of Computation for Massive Parallel System

A new approach to forecast forest fire danger using parallel computing operations in the computing systems with parallel architecture is the subject of this article. The parallel realization of the deterministic-probabilistic approach to estimate forest fire danger using the SPMD calculation model is presented. The parallel program is implemented using C programming language of high level with the Message Passing Interface (MPI). The computing experiments have been carried out by the Skif Cyberia multiprocessor cluster. The information on efficiency estimation and calculation acceleration is presented for this approach. The approach has been tested in the territory of the Timiryazevskiy forestry in Tomsk region (Russia). The typical results of forest fire danger estimation in the controlled forested territory are presented.

Engineering-Based Thermal CFD Simulations on Massive Parallel Systems

The development of parallel Computational Fluid Dynamics (CFD) codes is a challenging task that entails efficient parallelization concepts and strategies in order to achieve good scalability values when running those codes on modern supercomputers with several thousands to millions of cores. In this paper, we present a hierarchical data structure for massive parallel computations that supports the coupling of a Navier–Stokes-based fluid flow code with the Boussinesq approximation in order to address complex thermal scenarios for energy-related assessments. The newly designed data structure is specifically designed with the idea of interactive data exploration and visualization during runtime of the simulation code; a major shortcoming of traditional high-performance computing (HPC) simulation codes. We further show and discuss speed-up values obtained on one of Germany’s top-ranked supercomputers with up to 140,000 processes and present simulation results for different engineering-based thermal problems.

Sparc64 XIfx: Fujitsu's Next-Generation Processor for High-Performance Computing

Sparc64 XIfx, the latest high-performance computing processor, includes a 34-core processor and achieves 1.1 teraflops of peak performance. This chip is designed for massive parallel supercomputer systems that realize high performance for a wide range of real applications. As groundwork for exascale supercomputing, it has made major technological changes from the previous Sparc64 processor in the instruction set architecture, microarchitecture, memory modules, and embedded interconnect.

Runtime Comparison of CPU and GPU Using Portable Programming Models

Since increasing clock speeds are not enough to speed up computation, there exist several alternative options. One of them is parallelism. For some problems it is possible to use the graphics processor as a massive parallel system and gain high speedups. Since NVIDIA introduced the unified device architecture and AMD switched to the OpenCL programming model it is possible for everyone to achieve high speedups through massive parallel systems easily. In this paper CUDA and OpenCL are introduced and differences are shown. To point out that graphics processor can be used for common tasks too, there is a comparison on runtime of two different test cases. The results show why the problem size is a very important factor for decisions to make use of the massive parallelism.

Packet triggered prediction based task migration for network-on-chip

The development of IC technology makes Network-on-Chip (NoC) an attractive architecture for future massive parallel systems. Task migration optimize the overall communication performance of NoCs since the changing phases of execution make static task mapping insufficient. It is well-known that the communication behavior of many applications are predictable, which makes it feasible to use prediction to guide task migration. The triggering of activating a task migration is also important. In this paper, we first defined and analyzed predictabilities of applications, and then compared different ways of triggering for migration. We then modified the Genetic Algorithm (GA) based task remapping and proposed two other task migration algorithms: Simple Exchange (SE) and Benefit Assess (BA). A mechanism called node lock is also used to reduce unnecessary and costly migrations. Simulation results on real applications from PARSEC benchmark suites show that the SE, BA and GA algorithms can reduce 21.4%, 34.0% and 34.9% of number of hops, and 17.3%, 27.2% and 26.3% in terms of average latency respectively, compared with the system without task migration; BA and SE reduce 72.0% and 78.7% of migrations without significant performance degradation compared with GA, and the node lock mechanism can further remove 37.3% and 46.0% of migrations while achieving almost the same performance.

Are There Clouds in Our Blue Sky Research Programs?

Guest editorial As our industry pushes the frontiers of hydrocarbon recovery, complexity and risk management are increasingly pervasive dimensions of the landscape. High-performance computing (HPC) is providing new ways to address complexity and risk by opening more workflows to the “real time” world of operations. Cray supercomputers—named for inventor Seymour Cray—were introduced in the 1960s and became synonymous with this new breed of computer. Supercomputer performance is measured in floating point operations per second (FLOPS), which measures the number of calculations or instructions performed in a given time. This is generally used with an International System of Units (SI) prefix such as mega-, giga-, tera-, or peta- to describe the machine’s power or class. Today’s supercomputers are “petascale” machines, capable of processing one quadrillion (1015) FLOPS. However, they are the size of several rooms and require megawatts of power to operate, making them impractical and costly for all but the most esoteric and specialized problems. Computer clusters have become a more common way to build this processing power. By combining high-speed local networks and associated software, or “middleware,” massive parallel systems can be built that rival supercomputing power. Cloud computing is the latest extension of this concept in which computer resources, processing, and memory can be temporarily built into the required computing framework. Add in new job scheduling software, advanced virtualization techniques, and dynamic architecture configurations and you have the rapidly expanding high-performance computing discipline. Our industry is turning to high performance and cloud computing as a cost-effective way to build on-demand supercomputer capability for our most complex or intensive problems. At Baker Hughes, a three-tier approach has been designed to unlock this processing power for our research and development groups. The Dedicated Tier is an array of high-performance central processing units and high-memory servers that can provide massive total compute power joined into clusters with fast interconnects. This configuration is used mainly for applications that require dedicated, uninterrupted access to hardware and benefit from parallelization in a traditional, high-performance computing environment. The available performance capacity is often in the tens of teraFLOPS. The Opportunistic Tier is basically “cycle scavenging,” or the use of idle assets such as desktop computers and unused capacity on servers. Using Wake on LAN (WOL) technology, these computers can be powered on or off as needed. This approach is suitable for short-run applications with small footprints. It is useful where the synchronization among parallel jobs can be loosely coupled as well as when a user is far away from traditional HPC resources, but close to underused powerful desktops and servers. The available power scales linearly with the number of personal computers and nondedicated servers; it is not unusual to see power capabilities in the hundreds of teraFLOPS or more at a Fortune 250 company.

Biosecurity, microbial forensics and plant pathology: education challenges, overlapping disciplines and research needs

This article comments on aspects of functional overlapping of biosecurity, biosafety, bioterrorism, microbial forensics, plant pathology and education in a changing world showing the impact of increasing international trading, globalization and anthropogenic interventions. This commentary also introduces current research approaches such as, rapid collection devices, massive parallel systems and helicase dependent amplification applied to problems in biosecurity and microbial forensics.

Decongestants for clogged networks

Interconnection networks are a key element in a wide variety of systems: massive parallel processors, local and system area networks, clusters of PCs and workstations, and Internet Protocol routers. They are essential to high performance in the form of high-bandwidth communications, with low latency, "quality of service" (guaranteed service levels), efficient switching, and flexibility of network topology, as embodied in Myrinet, InfiniBand, Quadrics, Advanced Switching, and similar interconnects. But, despite all the advances that modem interconnects offer, congestion is a growing problem as "lossless" interconnection networksrdquo those that do not allow data packets to be discarded" come to the fore.

Recent trends in the marketplace of high performance computing

In this paper we analyze major recent trends and changes in the High Performance Computing (HPC) market place. The introduction of vector computers started the area of ‘Supercomputing’. The initial success of vector computers in the seventies was driven by raw performance. Massive parallel systems (MPP) became successful in the early nineties due to their better price/performance ratios, which was enabled by the attack of the ‘killer-micros’. The success of microprocessor based on the shared memory concept (referred to as symmetric multiprocessors (SMP)) even for the very high-end systems, was the basis for the emerging cluster concepts in the early 2000s. Within the first half of this decade clusters of PC’s and workstations have become the prevalent architecture for many HPC application areas on all ranges of performance. However, the Earth Simulator vector system demonstrated that many scientific applications could benefit greatly from other computer architectures. At the same time there is renewed broad interest in the scientific HPC community for new hardware architectures and new programming paradigms. The IBM BlueGene/L system is one early example of a shifting design focus for large-scale system. The DARPA HPCS program has the declared goal of building a Petaflops computer system by the end of the decade using novel computer architectures.

Interactive Visualization with Programmable Graphics Hardware

One of the main scientific goals of visualization is the development of algorithms and appropriate data models which facilitate interactive visual analysis and direct manipulation of the increasingly large data sets which result from simulations running on massive parallel computer systems, from measurements employing fast high-resolution sensors, or from large databases and hierarchical information spaces. This task can only be achieved with the optimization of all stages of the visualization pipeline: filtering, compression, and feature extraction of the raw data sets, adaptive visualization mappings which allow the users to choose between speed and accuracy, and exploiting new graphics hardware features for fast and high-quality rendering. The recent introduction of advanced programmability in widely available graphics hardware has already led to impressive progress in the area of volume visualization. However, besides the acceleration of the final rendering, flexible graphics hardware is increasingly being used also for the mapping and filtering stages of the visualization pipeline, thus giving rise to new levels of interactivity in visualization applications. The talk will present recent results of applying programmable graphics hardware in various visualization algorithms covering volume data, flow data, terrains, NPR rendering, and distributed and remote applications.