MASH Delta-sigma Modulator Research Articles

An 18-bit 2-2 MASH delta-sigma modulator for isolated amplifier

This paper presents an 18-bit 2-2 MASH delta-sigma modulator (DSM) for the isolated amplifier. Combining the cascade of integrators with feedforward (CIFF) structure and the cascade of integrators with feedback (CIFB) structure, the DSM effectively results in reduced harmonic distortion. Gain boost and slew rate (SR) boost techniques are used to enhance the performance of the first stage integrator. To reduce low-frequency noise, the chopper technique is adopted as well. The DSM was fabricated in a 0.18 μm CMOS process with an active area of 0.90 mm2, dissipating 29.70 mW under a 3.3 V supply with the Schreier figure-of-merit (FoMs) 170.00 dB. The 108.71 dB signal-to-noise and distortion ratio (SNDR) and 17.77 bits the effective number of bits (ENOB) are achieved by simulation in a 20 kHz bandwidth.

A Frequency-Tunable Fractional-N PLL for High-Energy Physics Experiments

A frequency tunable phase-locked loop (PLL) applied in high energy particle detector has been developed. In order to achieve high detection efficiency, high requirements are promoted for on-chip clock in CMOS pixel sensors, which requires high precision and low power consumption for the PLL. The proposed PLL employs a fractional-N frequency division structure. An LC voltage-controlled oscillator (LC-VCO) is used to generate the local clock. A third-order MASH sigma-delta (Σ - Δ) modulator is used to alleviate the quantization noise introduced by the fractional-N frequency divider. In order to further reduce the phase noise, pre-set and post-set binary frequency dividers are employed. In the prototype chip a low dropout regulator (LDO) is integrated to suppress the power supply noise. The PLL was designed and fabricated in a 180 nm CMOS process. It costs an area of 1.29 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a power of 8.1 mW at a 1.8 V power supply. The measured output frequency range is 400 - 530 MHz with the reference frequency of 25 - 35 MHz. The RMS jitter, integrated from 100 kHz to 100 MHz, is 4.8 ps at 526 MHz. The in-band spur is less than -61 dBc, and the phase noise at 1 MHz frequency offset is less than -113 dBc/Hz.

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators

Sturdy multi-stage noise-shaping (SMASH) delta-sigma modulators (DSMs) achieve high-order noise-shaping while significantly alleviating the mismatch issue between analog and digital transfer functions. Based on the SMASH architecture, we propose a methodology of synthesizing its continuous-time (CT) architecture from its discrete-time (DT) counterpart by using loop-filter connections. The proposed methodology circumvents the necessity of a direct extraction of the quantization noise from the early stages, which is problematic for CT architectures with high sampling rate. Moreover, the proposed method allows to intuitively compensate the CT SMASH for the excess loop delay (ELD). Furthermore, an input feedforward path is introduced into the second stage to eliminate the STF peaking induced by the ELD. A 2–2 SMASH topology is analyzed as a case study to demonstrate the synthesis methodology. Besides, we present derivations for determining loop-filter coefficients. Simulation results confirm the efficacy of the synthesis methodology for the SMASH topology.

Optimization of frequency settling time of PLL using 3rd MASH Sigma Delta Modulator

To reduce settling time of PLL, an attempt to optimize the parameters has been proposed in this paper. The transient responses of various Phase Locked Loop (PLL) frequency synthesizer have been comparied with their active and passive poles effect. These results are presented on a type-II 3rd order PLL frequency synthesizer employing a 3rd order MASH sigma delta modulator. The simulation results show the improved performance of the fractional frequency synthesizer for the communication system. These results have been simulated using Advanced Design System(ADS) tool.

High Resolution ADC for Ultrasound Color Doppler Imaging Based On MASH Sigma-Delta Modulator.

A high precision quantization ultrasound imaging system, capable of capturing small variances of the echo signal with a wide dynamic range, is important for producing accurate diagnostic outputs. Commercial ultrasound systems, typically utilizing 12 or 14 bits analog-to-digital converters (ADCs), lack the ability to measure blood flow deep inside the tissue and may be affected by surrounding tissue noise. In this study, we propose a newly designed ADC with over 20-bit resolution. The superior performance was achieved by shaping the quantization noise with a [Formula: see text] sigma-delta modulator (SDM), and filtering the shaped noise at high frequencies by a digital decimation filter. Designed in a mature 0.35 μm CMOS technology and powered by a 3.3 V voltage supply, the proposed SDM integrated circuits (IC) model achieved a signal to noise and distortion ratio (SNDR) of 109.5 dB, and an effective number of bits (ENOB) of 17.9-bit in an 8 MHz bandwidth. Eight identical SDMs were integrated onto one chip, and the entire layout occupied an area of 4.8 mm × 5 mm. A total of sixteen 8-channel SDM IC models were connected to all elements of the array transducer. Simulated performance with blood flow evaluation datasets using 12-bit and 20-bit ADCs demonstrates that the proposed 20-bit ADC provides superior overall performance on image contrast and estimation accuracy of the blood speed. Owing to these advantages, the 20-bit ADC shows promise for future development of ultrasound imaging systems, especially for color Doppler imaging.

A 16 Bits Sigma-Delta Modulator Applied in Gyroscope

In this paper, a 4th-order sigma-delta modulator applied in gyroscope is presented. This modulator adopts the 2-1-1 Multi stage noise shaping structure. The bandwidth of signal is 100 KHz, the over sample rate is 64, and sample frequency is 12.8MHz. By the MATLAB Simulink modeling and simulation, when the input signal is 100 KHz, the SNDR of the MASH ADC is 121.8dB, and the effective number of bit is 19.93 in ideal situation. After considering non-ideal factors, the SNDR is 111.6dB, the effective number of bit of ADC is 18.28. Compared with the ideal situation, the noise floor of PSD has increased 40dB. It explains that non-ideal factors have a significant effect on the performance of the sigma-delta ADC. The 4th-order MASH sigma-delta modulator has been implemented under 0.5 um CMOS process and simulated under Cadence. The final simulation results show that SNDR is 112.4 dB and effective number of bits (ENOB) is 18.6.

A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs

A dynamic comparator-based OTA is introduced as a replacement for a conventional OTA. It performs charge transfer in a switched-capacitor circuit by repeatedly evaluating the polarity of the differential input using a dynamic clocked comparator and injecting current pulses at the output to move the input voltage toward zero. The amplitude of the current pulse is reduced each time the input voltage crosses zero to provide fast but accurate settling of the output voltage. Dynamic comparator-based OTAs are applied to the design of a 1-1-1-1 MASH delta-sigma modulator. The 65-nm CMOS prototype achieves a 70.4 dB peak SNDR over a 2.5-MHz bandwidth while consuming 3.73 mW from a 1.2-V supply. The 276-fJ/conv-step FoM represents a four times improvement over previously-reported delta-sigma modulators using zero-crossing-based circuits or comparator-based switched capacitors. Because of the dynamic operation of the OTAs and discrete-time delta-sigma modulator architecture, both bandwidth and power consumption linearly scale with the sampling frequency without any reconfiguration of the modulator.

A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

We demonstrate a 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 mum CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 & dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).

Adaptive Correction of Errors in Residue Coupled MASH ΔΣ Modulators

MASH delta-sigma (ΔΣ) modulators consist of a cascade of several lower order single-loop modulators. In an ideal cascade, the quantization error from all but the last stage are digitally canceled. The drawback with a cascaded design is the requirement of precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This paper presents a new, adaptive improvement to the residue coupled MASH delta sigma modulator. The adaptive corrections significantly reduce the sensitivity to analog imperfections. The result is a simple MASH delta-sigma modulator with high precision. Simulations of a 1-1 MASH circuit structure with errors and corrections are included to confirm the theory.