MASH Architecture Research Articles

Incremental Analog-to-Digital Converters for High-Resolution Energy-Efficient Sensor Interfaces

Integrated sensor interface circuits require power-efficient high-accuracy data converters. In many applications, the best choice is to use incremental A/D converters (IADCs) incorporating extended counting. In this paper, we discuss the operation and design of IADCs, including single-loop and MASH architectures. When using a direct-feed-forward modulator, the IADC accumulates the residue voltage, and it is easily to implement a hybrid scheme of extended counting. Several hybrid schemes are review and discussed. A multi-step extended counting scheme is discussed for high-resolution power-efficient conversion. Optimal trade-off between high order and high oversampling ratio is critical for energy efficiency. A two-step IADC is discussed, which extends the performance of an $N$ th-order IADC close to that of a $(2N\!-\!1)$ th-order IADC, with reduced power. An implemented device uses the circuitry of a second-order IADC (IADC2) to achieve a performance close to that of a third-order IADC. The two-step operation can be extended to multi-step one, and the SQNR performance can be increased significantly. The two-step operation can be extended to multi-step operation, which can boost up the order of SQNR and further improve the energy efficiency drastically.

A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

We demonstrate a 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 mum CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 & dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).

A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. In multi-standard design, sigma-delta based ADC is one of the most popular choices. To this end, in this paper we present cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order ∑-Δ ADC) is used to achieve a peak SNDR of 88dB with over-sampling ratio of 160 for a bandwidth of 200KHz and for WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB peak SNDR with over-sampling ratio of 16 for a bandwidth of 2MHz. Finally, a 2-2-2 cascaded MASH architecture with 4-bit in the last stage is proposed to achieve a peak SNDR of 58dB for WLAN for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be made inactive to achieve low power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.

Dynamic Range Improvement of Multistage Multibit Modulator for Low Oversampling Ratios

This paper presents an improved architecture of the multistage multibit sigma-delta modulators (ΣΔMs) for wide-band applications. Our approach is based on two resonator topologies, high-Q cascade-of-resonator-with-feedforward (HQCRFF) and low-Q cascade-of-integrator-with-feedforward (LQCIFF). Because of in-band zeros introduced by internal loop filters, the proposed architecture enhances the suppression of the in-band quantization noise at a low OSR. The HQCRFF-based modulator with single-bit quantizer has two modes of operation, modulation and oscillation. When the HQCRFF-based modulator is operating in oscillation mode, the feedback path from the quantizer output to the input summing node is disabled and hence the modulator output is free of the quantization noise terms. Although operating in oscillation mode is not allowed for single-stage ΣΔM, the oscillation of HQCRFF-based modulator can improve dynamic range (DR) of the multistage (MASH) ΣΔM. The key to improving DR is to use HQCRFF-based modulator in the first stage and have the first stage oscillated. When the first stage oscillates, the coarse quantization noise vanishes and hence circuit nonidealities, such as finite op-amp gain and capacitor mismatching, do not cause leakage quantization noise problem. According to theoretical and numerical analysis, the proposed MASH architecture can inherently have wide DR without using additional calibration techniques.

An Efficient>tex<$Delta Sigma $>/tex<ADC Architecture for Low Oversampling Ratios

As the demand for /spl Delta//spl Sigma/ (delta-sigma) analog-to-digital converters (ADCs) with higher bandwidth and higher signal-to-noise ratio (SNR) increases, designers have to look for efficient structures with low oversampling ratio (OSR). The Leslie-Singh or M-0 MASH architecture is often used in such applications. Based on this architecture, a reduced-sample-rate structure was introduced, which needs less chip area and power, but increases the noise floor. This paper describes a modification of the reduced-sample-rate structure which realizes an optimized transfer function, and avoids an SNR loss. In fact, it increases the SNR for high-order modulators. The method can also be applied to one-stage modulators. Simulation results for different MASH ADCs and sensitivity analysis verify the usefulness of the proposed technique.

High Dynamic Range Design for ΣΔM with Wide Input Ranges

A new design algorithm is introduced to improve the input ranges of Sigma-Delta Modulation (ΣΔM). Modified digital error correction techniques are proposed and employed to carry out the wide range DAC of a ΣΔ modulator. This design algorithm includes the advantages from both single-bit ΣΔM and multi-bit ΣΔM. This paper utilizes a second order lowpass ΣΔ modulator as an explanatory example to demonstrate our design process as well as the performance improvement. The analytical results from a quasilinear model are described to offer a theoretical explanation of the system performance. This algorithm can also be applied to bandpass and MASH architectures.

High-order single-stage single-bit oversampling A/D converter stabilized with local feedback loops

A new method for the stabilization of high-order (>2) single-stage single-bit oversampling A/D converters is proposed. In this approach, the stability of the modulator is achieved by preventing any unbounded increase in the internal node-voltages through the insertion of local feedback signals inside the modulator loop. In the past, absolute bounds for stability have been derived for the first-order converter. This property is exploited in stabilizing a higher order loop by activating local first-order loops as soon as the internal integrators overload. With local feedback, individual integrators are prevented from saturating and the output voltages are within the proper bounds. The error caused by the local feedback signals is cancelled by feeding these signals through alternate signal paths, in a way similar to the quantization noise cancellation mechanism in a MASH architecture. Since the frequency of overloading can be made very low by proper design, the effect of imperfect cancellation due to mismatches in the two signal paths caused by the modulator nonidealities is quite small. Hence, compared to the inherently stable MASH architectures, the proposed approach achieves stability and is yet much less sensitive to component mismatches. In a sampled data environment where the integrator is realized using op amps, this translates into a low op amp gain requirement. Simulation results confirm that third order modulators using op amps with gain as low as 50 achieve a peak signal-to-noise ratio (SNR) of about 83 dB with an oversampling ratio of 64. This is less than 1 dB from the SNR achieved with infinite op amp gain. >