Memory Mapping Research Articles

컬러와 혈관징후패턴 코드 생성에 의한 공막진단시스템 구현

The paper describes the scleral diagnostic system implementation for human eyes by using the scleral color code and vessels sign pattern code generations. The system is based on the high performance DSP image signal processor, programmable gain control for preprocessing and RISC SD frames storage. RGB image signals are optimized by PGC, the edge image is detected form the gray image converted. The processing algorithms are executed by scleral color code generation and scleral vessels sign pattern code creation for discriminating and matching. The scleral symptomatic color code is generated by YCbCr values at memory map tolerated and the vessel sign pattern code is created by digitizing the 24 clock and 13 ring zones, overlay matching and tolerances. The experimental results for performance are that the system runs 40ms, and the color and pattern for diagnostic errors are around 20% and 24% on average. The system and technique enable a scleral diagnosis with subdividing the patterns and patient database.

High-Performance Computer-Generated Hologram by Optimized Implementation of Parallel GPGPUs

We propose a new development for calculating a computer-generated hologram (CGH) through the use of multiple general-purpose graphics processing units (GPGPUs). For optimization of the implementation, CGH parallelization, object point tiling, memory selection for object point, hologram tiling, CGMA (compute to global memory access) ratio by block size, and memory mapping were considered. The proposed CGH was equipped with a digital holographic video system consisting of a camera system for capturing images (object points) and CPU/GPGPU software (S/W) for various image processing activities. The proposed system can generate about 37 full HD holograms per second using about 6K object points.

Hemispheric bases for emotion and memory.

Hemispheric bases for emotion and memory.

A Mapping of Memory and Gravity’s Rainbow Fred Tomaselli’s Photocollage and Spectator’s View

A Mapping of Memory and Gravity’s Rainbow Fred Tomaselli’s Photocollage and Spectator’s View

NUMA-Aware Multicore Matrix Multiplication

A user-level scheduling along with a specific data alignment for matrix multiplication in cache-coherent Non-Uniform Memory Access (ccNUMA) architectures is presented. Addressing the data locality problem that could occur in such systems potentially alleviates memory bottlenecks. We show experimentally that an agnostic thread scheduler (e.g., OpenMP 3.1) from the data placement on a ccNUMA machine produces a high number of cache-misses. To overcome this memory contention problem, we show how proper memory mapping and scheduling manage to tune an existing matrix multiplication implementation and reduce the number of cache-misses by 67% and consequently, reduce the computation time by up to 22%. Finally, we show a relationship between cache-misses and the gained speedup as a novel figure of merit to measure the quality of the method.

A new memory mapping mechanism for GPGPUs’ stencil computation

When optimizing performance on a GPU, control flow divergence of threads in one warp can make up the possible performance bottlenecks. In our hand-coded GPU stencil computation optimization, with a view to remove this control flow divergence brought by conventional mapping method between global memory and shared memory, we devise a new mapping mechanism by modeling the coalesced memory accesses of GPU threads and the aligned ghost zone overheads to remove conditional statements of the boundary XY-tile stencil computation points for improved performance. In addition, we utilize only one XY-tile loaded into registers in every stencil computation iteration, common sub-expression elimination and software prefetching to reduce overheads. Finally, detailed performance evaluation demonstrates that global memory access traffic is close to the idealized lower bound value through our optimized policies, that is to say, in every computed point of one XY-tile the memory access traffic is roughly 6 and 4 % more than 8 bytes per XY-tile point of the idealized lower bound memory access traffic in which ghost zone overheads are not taken into consideration on Tesla C2050 and Kepler K20X respectively.

Role of the Wada test and functional magnetic resonance imaging in preoperative mapping of language and memory: two atypical cases

The Wada test is an invasive procedure used to determine cerebral memory and language dominance as well as risk of cognitive deficits following neurosurgery. However, the potential risks of Wada testing have led some to consider foregoing Wada testing in candidates for resective epilepsy surgery with right hemispheric seizure onset. We present two atypical cases in which the Wada test showed unexpected memory and language lateralization. These cases underscore the importance of functional magnetic resonance in which imaging and Wada examination in right-handed individuals even when the lesion would not suggest atypical language representation.

MMap: Fast Billion-Scale Graph Computation on a PC via Memory Mapping.

Graph computation approaches such as GraphChi and TurboGraph recently demonstrated that a single PC can perform efficient computation on billion-node graphs. To achieve high speed and scalability, they often need sophisticated data structures and memory management strategies. We propose a minimalist approach that forgoes such requirements, by leveraging the fundamental memory mapping (MMap) capability found on operating systems. We contribute: (1) a new insight that MMap is a viable technique for creating fast and scalable graph algorithms that surpasses some of the best techniques; (2) the design and implementation of popular graph algorithms for billion-scale graphs with little code, thanks to memory mapping; (3) extensive experiments on real graphs, including the 6.6 billion edge YahooWeb graph, and show that this new approach is significantly faster or comparable to the highly-optimized methods (e.g., 9.5× faster than GraphChi for computing PageRank on 1.47B edge Twitter graph). We believe our work provides a new direction in the design and development of scalable algorithms. Our packaged code is available at http://poloclub.gatech.edu/mmap/.

Pattern Recognition of Subconscious Underpinnings of Cognition using Ultrametric Topological Mapping of Thinking and Memory

The author reviews the theory and practice of determining what parts of a data set are ultrametric. He describes the potential relevance of ultrametric topology as a framework for unconscious thought processes. This view of ultrametric topology as a framework that complements metric-based, conscious, Aristotelian logical reasoning comes from the work of the Chilean psychoanalyst, Ignacio Matte Blanco. Taking text data, the author develops an algorithm for finding local ultrametricity in such data. He applies that in two case studies. The first relates to a large set of dream reports, and therefore can possibly recall traces of unconscious thought processes. The second case study uses Twitter social media, and has the aim of picking up underlying associations. The author's case studies are selective in regard to names of people and objects, and are focused in order to highlight the principle of his approach, which is one of particular pattern finding in textual data.

Research on the Loading Pattern of Embedded System

With the development of information technology, ERTOS(Embedded Real-Time Operating System) not only has involved in the scientific research and engineering domains, but also has many affinities people's life. Loading pattern performance is the most important performance of Embedded Operating System. It needs dispatching all available resources to achieve real-time task. In order to correctly evaluate the performance of a real-time Embedded Operating System, we must be scientific, systematic approach to ERTOS study of the comprehensive performance and accurate testing. This article discusses three loading patterns and the layout of the memory map on the Flash, RAM and external storage media, with tested on hardware platform it description the advantages and disadvantages of this three loading pattern.

Fast Display Algorithm of Large Map File Based on Memory Mapping File Technique

This paper presents a Fast display Algorithm of large Map File based on memory mapping file technique, designing for reducing the number of pointer moves and the data in memory scheduling ,The algorithm uses a memory-mapped file access operation of a large-scale map file to resolve the problem of traditional file processing methods, which can not read more than 2G map image file; combined image pyramid technology to apply different resolutions depending on the display requirements map image, in order to achieve the purpose of roaming quickly. The experiment and analysis results show that the algorithm is able to achieve the best resolution real-time roaming of large-scale digital map.

Towards Scalable Graph Computation on Mobile Devices.

Mobile devices have become increasingly central to our everyday activities, due to their portability, multi-touch capabilities, and ever-improving computational power. Such attractive features have spurred research interest in leveraging mobile devices for computation. We explore a novel approach that aims to use a single mobile device to perform scalable graph computation on large graphs that do not fit in the device's limited main memory, opening up the possibility of performing on-device analysis of large datasets, without relying on the cloud. Based on the familiar memory mapping capability provided by today's mobile operating systems, our approach to scale up computation is powerful and intentionally kept simple to maximize its applicability across the iOS and Android platforms. Our experiments demonstrate that an iPad mini can perform fast computation on large real graphs with as many as 272 million edges (Google+ social graph), at a speed that is only a few times slower than a 13″ Macbook Pro. Through creating a real world iOS app with this technique, we demonstrate the strong potential application for scalable graph computation on a single mobile device using our approach.

Inferring memory map instructions

We describe the problem of inferring a set of memory map instructions from a reference trace, with the goal of minimizing the number of such instructions as well as the number of unreferenced but mapped storage locations. We prove the related decision problem NP-complete. We then present and compare the results of two heuristic approaches on some actual traces.

Algorithmic GPGPU Memory Optimization

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

Parallel Compression and Decompression of DNA Sequence Reads in FASTQ Format

Large volumes of short reads of genomic data are generated by high-throughput sequencing instruments. The FASTQ format is widely accepted as the input format of genomic reads and has presented challenges in data storage, management, and transfer. The performance of this type of serial algorithms such as G-SQZ and DSRC is limited by the single processor and the memory in a single computer. Utilizing data parallelism, the circular dual queues of buffers, memory mapping integrated with superblocks, pipeline parallelism with multi threads, and so on, we present the parallel compression and decompression methods for DNA sequence reads in FASTQ format based on the parallel computer architectures of the cluster and the SMP. Experimental results for the parallel DSRC algorithm clearly show the efficiency of using the powerful computing resources from multi computing nodes and multi cores of each node. The speedups vary from 46 to 62 for parallel compression and vary from 40 to 58 for parallel decompression by using 10 nodes of the cluster in Tianhe-1A super computer. Test results on the SMP machine are also pleasant. The methods could be applied to any serial compressing algorithms of DNA sequence reads in FASTQ format only if they have the traits of index and superblocks.

Caputo standard α-family of maps: fractional difference vs. fractional.

In this paper, the author compares behaviors of systems which can be described by fractional differential and fractional difference equations using the fractional and fractional difference Caputo standard α-Families of maps as examples. The author shows that properties of fractional difference maps (systems with falling factorial-law memory) are similar to the properties of fractional maps (systems with power-law memory). The similarities (types of attractors, power-law convergence of trajectories, existence of cascade of bifurcations and intermittent cascade of bifurcations type trajectories, and dependence of properties on the memory parameter α) and differences in properties of falling factorial- and power-law memory maps are investigated.

Contrapuntal Memories? Remembering the Holocaust in a Post-9/11 World

This essay traces the post-9/11 mapping of Holocaust memory throughout the United States as it converges with the U.S.-led war on terror and the memorialization of September 11th at the World Trade Center. For instance, comments made by George W. Bush during the 2008 U.S. presidential campaigns equated Barack Obama's advocacy for communications between the U.S. and former Iranian Prime Minister, Mahmoud Ahmadinejad, to the appeasement of Hitler at the onset of WWII. For scholars of memory, the (geo)political importance of such exchanges should not be taken lightly or go unnoticed. Building upon geographies of memory, as well as recent texts within Memory Studies, this essay theorizes the post-9/11 spatial diffusion of Holocaust memory as it is evoked and disseminated in relation to, and within, other landscapes of memory in order to shape the (geo)political present.

Timing & Time Perception Reviews: Opening the Door to Theoretical Discussions of Consciousness, Decision-Making, Multisensory Processing, Time Cells and Memory Mapping … to Name But a Few Issues of Relevance to Temporal Cognition

The journal Timing & Time Perception (Brill Publishers) was initiated with the realization that the study of ‘timing and time perception’ is growing exponentially with interest from fields as diverse as cognitive science, computer science, economics, philosophy, psychology, robotics, and neuroscience … to name just a few. As with any scientific endeavor, once a sufficient empirical base has been established it becomes both necessary and desirable to support such a rapidly growing enterprise with a platform for publishing integrative and multidisciplinary reviews. We are pleased to announce that Timing & Time Perception Reviews (a joint publication of the University of Groningen and Brill Publishers) is being launched as a diamond open-access journal with that goal firmly in mind. Some of the highlights of the inaugural issue are presented in our editorial along with examples of the types of ideas we would like to see developed in future submissions to the journal.

„Nagie życie” w zakładach dla psychicznie i nerwowo chorych pod rządami nazistów

The principal hypothesis of our inquiry states that the mechanisms of power and controlling human life, practiced by the Nazis during WW 2, reflected the modern approach to the human defined in the categories of life unworthy of life. The studies conducted hitherto in the context of the above hypothesis focus on the sites which in the wake of commemorating the extermination are treated as symbols of the genocide industry, such as the Auschwitz-Birkenau death camp. In turn, this article aims to investigate the validity of the hypothesis with regards to a site which so far has not been considered in cultural studies – (for example the Hospital for the Mentally Ill “Dziekanka” in Gniezno – in addition, we treat this hospital as the exemplification of the wider ideological, political, economic phenomenon). I wish to show that the phenomena of reducing and destroying human life, which held no value for the authority, was virtually identical regardless of the place where the extermination took place. Thus, we will establish a new point on the map of memory of the victims of Nazi policies, a site where the annihilation was carried out, at the same time demonstrating the particular features associated with that particular space. The “might” of the German authority during World War 2 was founded on tremendous attention to detail; consequently, that which took place in the sites of mass extermination proceeded in much the same way in those places which are now hardly remembered.

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications

High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm2 in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.