Mapping Entries Research Articles

CCFTL: A novel continuity compressed page-level flash address mapping method for SSDs

Given the distinctive characteristics of flash-based solid-state drives (SSDs), such as out-of-place update scheme, as compared to traditional block storage devices, a flash translation layer (FTL) has been introduced to hide these features. In the FTL, there is an address translation module that implements the conversion from logical addresses to physical addresses. However, existing address mapping algorithms currently fail to fully exploit the mapping information generated by large I/O requests. First, based on this observation, we propose a novel continuity compressed page-level flash address mapping method (CCFTL). This method effectively compresses the mapping relationship between consecutive logical addresses and physical addresses, enabling the storage of more mapping information within the same mapping cache size. Next, we introduce two-level LRU linked list to mitigate the issue of compressed mapping entry splitting that arises from handling write requests. Finally, our experiments show that CCFTL reduced average response times by 52.67%, 16.81%, and 12.71% compared to DFTL, TPFTL, and MFTL, respectively. As the mapping cache size decreases from 2 MB to 1 MB, then further decreases to 256 KB, 128 KB, and eventually down to 64 KB, CCFTL experiences an average decline ratio of less than 3% in average response time, while the other three algorithms show an average decline ratio of 9.51%.

CRFTL: Cache Reallocation-Based Page-Level Flash Translation Layer for Smartphones

Because of its outstanding performance, NAND flash memory in the form of embedded flash drives like Universal Flash Storage (UFS) has been widely used in the modern smartphones. As the core software in UFS, the flash translation layer (FTL) is essential to the performance improvement of UFS. To consider all workloads, a balanced and fixed mapping cache allocation scheme is used in the existing FTLs. Confronted with frequent changes of I/O request patterns of applications in smartphones, the existing FTLs with the fixed mapping cache allocation scheme could not perform well. To consider the I/O characteristics of smartphones, a novel cache reallocation-based page-level flash translation layer, called CRFTL, is proposed in this paper. Through analyzing the life cycle of I/O requests of applications in smartphones, CRFTL stores the mapping entries of I/O requests with different life cycles in different mapping cache structures. CRFTL can be aware of the inner states of NAND flash memory and I/O request patterns, and adaptively adjusts the cache space allocation of the mapping cache structures by applying the approach combining the heuristics and reinforcement learning algorithms. The experimental results show that the performance of our proposed CRFTL is better than that of existing FTLs.

HCFTL: A Locality-Aware Flash Translation Layer for Efficient Address Translation

In modern solid-state drives (SSDs), a flash translation layer (FTL) is the core engine performing the logical-to-physical address translations. However, the increasing capacity of SSDs requires a large DRAM space to hold the mapping table in a page-level FTL. Due to the limited size of built-in DRAM, existing FTL schemes selectively cache some active mapping entries in DRAM, while store the entire mapping table on flash. However, the low cache hit ratio introduced by the traditional mapping entry eviction policy degrades the access performance of SSDs. In this article, we propose a novel FTL, hot-clusterity FTL (HCFTL), to improve the hit ratio of cached mapping table (CMT) of SSDs with limited cache space. HCFTL clusters mapping entries, which are newly evicted from the cache, into dynamic translation pages (DTPs). Reading entries from DTPs will increase the CMT hit ratio due to spatial and temporal localities. Because the logical page numbers (LPNs) in a DTP are not consecutive, we introduce two different efficient index structures to speedup the lookup of mapping entries in DTPs. Furthermore, to make the DTP index highly accurate, we additionally allocate an auxiliary cache to buffer the mapping entries newly evicted from CMT, and produce dynamic pages with minimum difference between the maximal and the minimal LPNs of entries in those pages. Our experiments show that HCFTL can improve the CMT hit ratio by up to 41.1% and decrease the system response time by up to 33.3%, compared to baseline FTL schemes.

Dual Locality-Based Flash Translation Layer for NAND Flash-Based Consumer Electronics

NAND flash memory shows prominent performance, so it has been used as storage devices of consumer electronics, such as the smart phones and tablet personal computers. As the storage management software of NAND flash memory, the page-level flash translation layer (PLFTL) owns very high I/O access performance for consumer electronics. As an improved version of PLFTL, the demand-based PLFTL selectively keeps active mapping entries in the DRAM (Dynamic Random Access Memory) and the demand-based PLFTL mainly considers the temporal locality of workloads. However, the spatial locality also appears in many workloads. To exploit the temporal locality and spatial locality of workloads, a novel dual locality-based FTL (DL-FTL) is proposed in this paper. DL-FTL uses the sequential cache mapping state table (S-CMST) and sequential physical address cache mapping table (SPA-CMT) to process the sequential requests. To decrease the update counts of translation pages, the mapping entries that are evicted from S-CMST will be written back to NAND flash memory using a batch update strategy. The experimental results show that our proposed DL-FTL raises the cache hit ratio by up to 66.39% and reduces the system response time by up to 21.64% on average, compared with the demand-based PLFTL.

GFTL: Group-Level Mapping in Flash Translation Layer to Provide Efficient Address Translation for NAND Flash-Based SSDs

NAND flash memory has been widely used as data storage devices in consumer electronics, such as tablet computers and smart phones. Logical-to-physical address translation is important for improving the performance of NAND flash-based SSDs. Even though keeping the mapping table in a DRAM can boost the address translation, it is already infeasible to do this as the capacity of SSDs keeps increasing and only a limited part of DRAM will be used as the mapping cache. Orthogonal to the demand-based page-level FTLs, we develop a novel group-level mapping which divides the whole SSD into multiple equal-size groups. To map a logical-page-number to a physical-page-number, it will be translated into a group number and an offset. The group number can be obtained via calculation, and the offset will be retrieved from a recorded mapping entry which can correspond to any position within a group. Group-level mapping reduces the size of mapping table while obtaining the similar flexibility as the page-level mapping. We also design an effective group-level FTL (GFTL) with a block pool management approach. Our simulations show that GFTL improves the hit ratio of mapping cache and thus reduces the average response time.

DSTL

Shingled magnetic recording (SMR) is regarded as a promising technology for resolving the areal density limitation of conventional magnetic recording hard disk drives. Among different types of SMR drives, drive-managed SMR (DM-SMR) requires no changes on the host software and is widely used in today’s consumer market. DM-SMR employs a shingled translation layer (STL) to hide its inherent sequential-write constraint from the host software and emulate the SMR drive as a block device via maintaining logical to physical block address mapping entries. However, because most existing STL designs do not simultaneously consider the access pattern and the data update frequency of incoming workloads, those mapping entries maintained within the STL cannot be effectively managed, thus inducing unnecessary performance overhead. To resolve the inefficiency of existing STL designs, this article proposes a demand-based STL (DSTL) to simultaneously consider the access pattern and update frequency of incoming data streams to enhance the access performance of DM-SMR. The proposed design was evaluated by a series of experiments, and the results show that the proposed DSTL can outperform other SMR management approach by up to 86.69% in terms of read/write performance.

HyFAT: Affordable Hybrid Fast Address Translating Device Driver for Multichannel-Based Flash Devices

Artificial intelligence (AI)-based consumer electronic (CE) devices generate massive amounts of accumulated hot data. Persisting this data into such devices’ storage media like the universal flash storage (USF) becomes an issue for flash storage system to manage hot data optimally. Consequently, efforts have been made to support many CE applications and achieve high performance and scalability storage in CE devices. However, it is challenging to find a compatible flash translation layer (FTL) for such flash devices, which can efficiently handle frequent updates imposed by the incoming hot data. Moreover, FTL should be able to handle the hot multimedia data that induces cache-miss penalties which in-turn degrades our flash storage performance. This paper proposes a hybrid flash device for fast address translations called HyFAT which is workload-compatible. HyFAT improves device performance and efficiently manages the combined QuadLevel cell (QLC) for data storage and scalability with SingleLevel cell (SLC) for fast mapping entry storage. The experimental results with realistic workloads show that our approach can improve device performance throughput by 18% on average, compared to traditional DFTL and RFTL.

A Correlation-Aware Page-Level FTL to Exploit Semantic Links in Workloads

NAND Flash based Solid State Disks (SSDs) are gaining tremendous popularity in today’s storage market due to their unique erase-before-write feature. The Flash Translation Layer (FTL) in the SSDs redirects the incoming writes to a free physical address and manages a logical to physical address mapping table. However, this induces significant performance degradation to the SSDs. One of the main reasons is that current cache management in FTLs is mainly optimized for the temporal or spatial locality. However, because of multiple levels of data buffers in the whole storage architecture, the locality of internal disk I/O is relatively low. What’s more, the increasing capacity of SSD not only generates large mapping tables, but also imposes high pressure on the efficiency of page-level address mapping. To overcome this limitation, we propose Correlation-Aware Page-level FTL, a.k.a CPFTL, which exploits I/O correlations in the workloads. In CPFTL, we develop a correlation-aware mapping table based on the correlation in read operations. We then build a correlation prediction table to support fast mapping entry lookup in the correlation-aware mapping table. Finally, we split read and write caches and build a skew-aware dirty entry index to improve the cache hit ratio and reduce the garbage collection overhead. Our emulator and prototype are open-sourced at: https://github.com/janzhou/SSD-Emulator . The experimental results show that CPFTL can reduce the average response time by 63.4 percent for read dominant workloads and 32.9 percent for transaction workloads.

An Adaptive Read-Write Partitioning Flash Translation Layer Algorithm

The classic demand-based flash translation layer (DFTL) algorithm is well-known since it can solve the contradiction between mapping flexibility and the size of mapping cache by dynamically loading mapping entries. However, DFTL failed to utilize the spatial locality and hot-cold characteristics of the request and had an inefficient mapping entry eviction scheme. This paper proposes an adaptive read-write partitioning flash translation layer algorithm (ARWFTL). First, the cache mapping table (CMT) is divided into the read CMT and the write CMT. The size of the two can be adaptively adjusted by sensing the characteristics of the upper workload and the read-write latency of the underlying flash page. Second, a priority eviction window is set at the tail of the write CMT to evict the clean mapping entry firstly. When there is no clean mapping entry in the priority eviction window, the tail mapping entry and other mapping entries that belong to the same translation page are clustered to write back into the translation page. Then, other written back mapping entries are set to be clean and the tail mapping entry is evicted. Third, a hot data window is set at the head of the write CMT to recognize the hot and cold data of write requests. Then, the hot and cold data are stored in different data blocks of flash to avoid hot and cold data entanglement and reduce valid page migrations in garbage collection. Experimental results show that, compared with DFTL, ARWFTL can reduce the translation page write counts, the valid page migration counts, the block erase counts, and the average response time by 92.8%, 47.7%, 31.7%, and 31.4%, respectively. In addition, ARWFTL is also superior to the other recent DFTL-based improved algorithms, and even exceeds the pure page-level FTL in some indicators.

Assessing the quality of single particle reconstructions by atomic model building.

The 2015/2016 Map Challenge challenged cryo-EM practitioners to process a series of publicly available cryo-EM datasets. As part of the challenge, metrics needed to be developed to assess and compare the quality of the different map submissions. The most common metric for assessing maps is determining the resolution by Fourier shell correlation (FSC), but there are well known instances where the resolution can be misleading. In this manuscript, we present a new approach for assessing the quality of a map by determining the map "modelability" rather than on resolution. We used the automated map tracing and modeling algorithms in Rosetta to generate populations of models, and then compared the populations between different map entries by the Rosetta score, RMSD to a reference model provided by the map challenge, and by pair-wise RMSDs between different models in the population. These metrics were used to determine statistically significant rankings for the map challengers for each dataset. The rankings revealed inconsistencies between the resolution by FSC, emphasized the importance of the interplay between number of particles contributing to a map and map quality, and revealed the importance of software familiarity on single particle reconstruction results. However, because multiple variables changed between map entries, it was challenging to derive best practices from the map challenge results.

Karnaugh-Map Utility in Medical Studies: The Case of Fetal Malnutrition

This paper advocate and demonstrates the utility of the Karnaugh map, as a pictorial manual tool of Boolean algebra, in the exploration of medical problems as exemplified herein by the problem of Fetal Malnutrition (FM). The paper briefly introduces the FM problem, and specifies four metrics or tests used frequently in its study. Clinical data collected about these metrics (as continuous variables or dichotomized versions thereof) are conventionally treated via statistical methods. The Karnaugh map serves as a convenient way for aggregating the set of clinical data available into a pseudo-Boolean function. The map can be used to produce a two-by-two contingency matrix (confusion matrix or frequency matrix) that relates an assessed test or metric to a reference or standard one. Each of these two metrics can be any of the map variables or a function of some or all of these variables. While the map serves in this capacity as a supplement or aid to statistical methods, it is also useful for certain non-statistical methods (specifically Boolean ones). The paper shows how the map entries can be dichotomized via an appropriate threshold for use in Boolean Analysis (BA), which can be conducted despite the lack of a gold standard. The map also implements Qualitative Comparative Analysis (QCA) for the given clinical data. The map variable-handling capability does not pose as a shortcoming for either BA or QCA, since the number of variables involved (not only herein but in other typical medical problems as well) is relatively small. The concepts and methods introduced herein are demonstrated through application to the aforementioned set of clinical data for the FM problem, and can be extended to a wide variety of medical problems.

Dypermin: Dynamic permission mining framework for android platform

The Android architecture introduces to the application layer a permission based access control model for restricting access to sensitive phone resources. In this model the access to Application Programming Interfaces (APIs) is protected through permissions defined by the Android OS. The developers in order to utilize protected API methods must declare, in the application’s manifest, the appropriate permissions. The “relation” between framework method and a permission can be found through Android’s documentation. However, not only documentation may accidentally lack information but also Android features undocumented and hidden API methods. Undoubtedly a major challenge for researchers today, is the accurate identification of API methods and permissions pairs, which compose the permission map for the Android framework.This paper introduces Dypermin; a transparent framework for compiling the Android permission map without requiring any modification to the underlying operating system. To achieve that, Dypermin capitalizes on intrinsic properties of the Android framework that is security exceptions during runtime and the availability of any protected API method through the Android framework, as well as on the advantages of Java reflection mechanism. Dypermin, in contrast to other related methods, validates itself as it relies on runtime information, meaning that it does not generate false positive map entries. Dypermin has been evaluated on different Android versions. The results have been compared with the respective results of other proposed methods in order to demonstrate Dypermin’s efficacy for compiling the Android permission map for any given version.

Understanding and Alleviating the Impact of the Flash Address Translation on Solid State Devices

Flash-based solid state devices (SSDs) have been widely employed in consumer and enterprise storage systems. However, the increasing SSD capacity imposes great pressure on performing efficient logical to physical address translation in a page-level flash translation layer (FTL). Existing schemes usually employ a built-in RAM to store mapping information, called mapping cache , to speed up the address translation. Since only a fraction of the mapping table can be cached due to limited cache space, a large number of extra flash accesses are required for cache management and garbage collection, degrading the performance and lifetime of an SSD. In this paper, we first apply analytical models to investigate the key factors that incur extra flash accesses during address translation. Then, we propose a novel page-level FTL with an efficient translation page-level caching mechanism, named TPFTL , to minimize the extra flash accesses. TPFTL employs a two-level least recently used (LRU) list with space-efficient optimizations to organize cached mapping entries. Inspired by the models, we further design a workload-adaptive loading policy combined with an efficient replacement policy to increase the cache hit rate and reduce the writebacks of replaced dirty entries. Finally, we evaluate TPFTL using extensive trace-driven simulations. Our evaluation results show that compared to the state-of-the-art FTLs, TPFTL significantly reduces the extra operations caused by address translation, achieving reductions on system response time and write amplification by up to 27.1% and 32.2%, respectively.

Exploiting Sequential and Temporal Localities to Improve Performance of NAND Flash-Based SSDs

NAND flash-based Solid-State Drives (SSDs) are becoming a viable alternative as a secondary storage solution for many computing systems. Since the physical characteristics of NAND flash memory are different from conventional Hard-Disk Drives (HDDs), flash-based SSDs usually employ an intermediate software layer, called a Flash Translation Layer (FTL). The FTL runs several firmware algorithms for logical-to-physical mapping, I/O interleaving, garbage collection, wear-leveling, and so on. These FTL algorithms not only have a great effect on storage performance and lifetime, but also determine hardware cost and data integrity. In general, a hybrid FTL scheme has been widely used in mobile devices because it exhibits high performance and high data integrity at a low hardware cost. Recently, a demand-based FTL based on page-level mapping has been rapidly adopted in high-performance SSDs. The demand-based FTL more effectively exploits the device-level parallelism than the hybrid FTL and requires a small amount of memory by keeping only popular mapping entries in DRAM. Because of this caching mechanism, however, the demand-based FTL is not robust enough for power failures and requires extra reads to fetch missing mapping entries from NAND flash. In this article, we propose a new flash translation layer called LAST++. The proposed LAST++ scheme is based on the hybrid FTL, thus it has the inherent benefits of the hybrid FTL, including low resource requirements, strong robustness for power failures, and high read performance. By effectively exploiting the locality of I/O references, LAST++ increases device-level parallelism and reduces garbage collection overheads. This leads to a great improvement of I/O performance and makes it possible to overcome the limitations of the hybrid FTL. Our experimental results show that LAST++ outperforms the demand-based FTL by 27% for writes and 7% for reads, on average, while offering higher robustness against sudden power failures. LAST++ also improves write performance by 39%, on average, over the existing hybrid FTL.

Ontology-based Change Propagation in Shareable Health Information Applications

One of the most important challenges to be ad-dressed when establishing an integrated smart health environ-ment is the availability of shareable health data and knowledge which standardize the interoperability of components within the environment. Health ontologies are commonly utilized to enable interoperability between applications in such environment. However, the dynamic nature of health knowledge causes the need for frequent changes in health ontologies which then must be propagated to the relevant applications. A change propagation method that can efficiently streamline the change management from an ontology to all the applications which reference to it is proposed. A component called a mapper is used to manage the mapping between application terms and ontology concepts. The mapper is aimed to maintain the applications’ access to the most up-to-date ontology concepts and to improve the semantic mapping between the application terms and the ontology concepts. Some rules are developed for the change propagation process. The evaluation of the method shows that the mapper can improve the mapping list in terms of: (i) correctness, by proposing a new mapping entry to substitute an existing one which is not valid anymore because ontology concept is deleted or changed;(ii) currency maintenance, by recommending a better mapping between an application term and a new ontology concept based on the similarity value between the term and the new concept.

On-Demand Block-Level Address Mapping in Large-Scale NAND Flash Storage Systems

The density of flash memory chips has doubled every two years in the past decade and the trend is expected to continue. The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping management. This paper proposes a novel Demand-based block-level Address mapping scheme with a two-level Caching mechanism (DAC) for large-scale NAND flash storage systems. The objective is to reduce RAM footprint without excessively compromising system response time. In our technique, the block-level address mapping table is stored in fixed pages (called the translation pages) in the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand address mapping entries. Meanwhile, by exploring both spatial locality and access frequency of workloads with another two caches, the second-level cache is designed to cache selected translation pages. In such a way, both the most-frequently-accessed and sequentially accessed address mapping entries can be stored in the cache so the cache hit ratio can be increased and the system response time can be improved. To the best of our knowledge, this is the first work to reduce the RAM cost by employing the demand-based approach on block-level address mapping schemes. The experiments have been conducted on a real embedded platform. The experimental results show that our technique can effectively reduce the RAM footprint while maintaining similar average system response time compared with previous work.

Blocking DoS Attack Traffic in Network with Locator/Identifier Separation

DoS attacks remain a most serious threat to the Internet currently, how to mitigate DoS attack is still an open issue. Besides, the current Internet faces serious scaling problems, and locator/identifier separation is widely recognized as a most promising solution for the future Internet. To block DoS attack traffic in network with locator/identifier separation, we propose a network layer defense system called BlockDoS. BlockDoS expands the mapping entries of the mapping system to store the block information, and enables any DoS attack victim to actively request the network to block unwanted traffic at tunnel routers. We implement a prototype of BlockDoS. The analysis and experiment results show that BlockDoS can block multi-million attackers’ traffic within tens of minutes, and the computing and storage costs added by BlockDoS won’t affect the performance of the mapping servers and tunnel routers.

The English Year: A Month-by-Month Guide to the Nation’s Customs and Festivals from May Day to Mischief Night (review)

Over the last few years Steve Roud has published a series of readable but authoritative reference works, starting with A Dictionary of English Folklore (with Jacqueline Simpson, 2001), continuing with the Penguin Guide to the Superstitions of Britain and Ireland (2003), and now the present work. They display an increasing level of magisterial authority which nevertheless serves to enlighten rather than intimidate the reader, and combines with a very common-sense and matter-of-fact approach to the subject matter, in a field that invites imagination and fancy to run riot. It is often tempting to skip the introduction to any book and plunge straight into the main text. I would advise against this here, however, as Rouds introduction not only sets the tone for the book, but is a model exposition of the reasons why an evidence based approach to customs is desirable, and a demonstration of the inadequacies of the aetiological legends that surround many of our customs. 'The vast majority, Roud writes (p. xiv), 'are simply fictitious tales that have been repeated often enough to take on the veneer of accredited fact. They are believed because they function well as stories, they are neat and plausible, and people like them Not only does Rouds introduction set the ground rules for an appreciation of the nature of custom that illumines the contents of the book, but he also includes a helpful note on 'The Calendar' which reminds us that even the mere counting of days is fraught with difficulty and complication. The book is arranged, naturally, in the order of the days of the year, and at the start of each month a useful 'month-to-view' calendar is supplied, highlighting the main festivals and customs described for the month. There is also an attempt at a geographical presentation, in a series of indexed maps, but this is not comprehensive: there are no map entries for Herefordshire, for example, whereas a check of the full index will reveal plenty of material that might have been mapped. The body of the text flows freely, with references and footnotes by and large relegated to a 'Sources' section at the end of the book, giving minimal but sufficient information for those who want to go back to the roots. Inevitably, a work such as this relies very heavily on its predecessors, from William Hone's Every-day Book of 1827, through the Folklore Society's compilations of an earlier age, Wright and Lones's three-volume British Calendar Customs: England of 1936-40, to more recent works such as Brian Shuel's 1985 book, The National Trust Guide to the Traditional Customs of Britain. A surprising omission is Blackburn and Holford-Strevens's Oxford Companion to the Year (1999). Authoritative as it is, Roud's book is largely a compilation from printed sources. This gives the inevitable feeling that what gets written about is what has already been written about. References to standard local works such those of Ella Leather for Herefordshire (1912) and Ethel Rudkin for Lincolnshire (1936) abound, and one wonders about the fate of customs in counties that have not had the benefit of their own folklorist.

SOFTWARE PACKAGES FOR STUDYING DIFFUSION PATHWAYS OF GASES IN PROTEINS

Mapping entry and exit pathways of gases in proteins is now carried out using a combination of crystallographic, spectroscopic and computational techniques. Recent technological advances have brought about a broad range of software packages that can map diffusion pathways in several different classes of proteins, the results of which can be verified experimentally. We review some of the software packages used to study diffusion pathways in different proteins and discuss some common applications. It is anticipated that this review will serve as a useful resource in choosing the software package best suited to one's need to study a problem on diffusion pathways for diatomic molecules while providing the necessary background for this purpose.

The mapping of spectral coefficients and its application

A new geometric format, the r j spectral coefficient map, is here introduced, the entries in which are the spectral coefficient values by which any combinatorial function may be defined. Although similar in outline to the classic Karnaugh map, the r j map entries are each global parameters of the given function, unlike the discrete binary values plotted on a Karnaugh map. It is shown that the r j map construction may readily be used to generate the spectral coefficient values for any given function, and to transform spectral coefficient values back to the conventional binary-valued domain. Further, all the known analysis and synthesis procedures using spectral data may be implemented in the map format, the geometrical layout of which provides a ready insight into the required coefficient relationships.