Many-core Systems Research Articles

Adaptive random-grid and progressive color secret sharing with CNN super-resolution on a many-core system

This study introduces an innovative method combining Convolutional Neural Networks (CNN) with random grid generation for enhanced visual secret sharing. Our approach supports color images, reduces processing time, and offers non-pixel expansion and flexible share combinations. Utilizing GPU computation, it significantly improves practicality and efficiency by operating in a feed-forward manner, avoiding complex optimization. Experimental results demonstrate superior metrics: maximum PSNR of 32 dB, 99% NCC correlation with benchmarks, 2.9% NAE, and SSIM of 98%. We achieve substantial speedups– 493 × for 256 × 256 and 3145 × for 1024 × 1024 images–compared to sequential models. The scheme exhibits robustness against attacks, evidenced by CMY component and share histogram similarities, and scalability shown in combinatorial explosion visualization. These findings underscore the efficacy and efficiency of our approach, advancing secure image sharing applications significantly.

Neural-network-based hardware trojan attack prediction and security defense mechanism in optical networks-on-chip

Optical networks-on-chip (ONoCs) have emerged as a compelling platform for many-core systems owing to their notable attributes, including high bandwidth, low latency, and energy efficiency. Nonetheless, the integration of microring resonators (MRs) in ONoCs exposes them to vulnerabilities associated with hardware trojans (HTs). In response, we propose an innovative strategy that combines deep-learning-based HT attack prediction with a robust security defense mechanism to fortify the resilience of ONoCs. For HT attack prediction, we employ a multiple-inputs and multiple-outputs long short-term memory neural network model. This model serves to identify susceptible MRs by forecasting alterations in traffic patterns and detecting internal faults within optical routing nodes. On the defensive front, we introduce a fine-grained defense mechanism based on MR faults. This mechanism effectively thwarts HTs during the optical routing process, thereby optimizing node utilization in ONoCs while concurrently upholding security and reliability. Simulation outcomes underscore the efficacy of the proposed HT attack prediction mechanism, demonstrating high accuracy with a loss rate of less than 0.7%. The measured mean absolute error and root mean squared error stand at 0.045 and 0.07, respectively. Furthermore, when compared to conventional coarse-grained node-based defense algorithms, our solution achieves noteworthy reductions of up to 16.2%, 43.72%, and 44.86% in packet loss rate, insertion loss, and crosstalk noise, respectively.

X-OpenMP — eXtreme fine-grained tasking using lock-less work stealing

Processors with 100s of threads of execution are among the state-of-the-art in high-end computing systems. This transition to many-core computing has required the community to develop new algorithms to overcome significant latency bottlenecks through massive concurrency. However, implementing efficient parallel runtimes that can scale up to high concurrency levels with extremely fine-grained tasks remains a challenge. Existing techniques do not scale to a large number of threads due to the high cost of synchronization in concurrent data structures. We present a thorough analysis of various synchronization mechanisms including mutex, semaphore, spinlock and atomic fetch-and-add that are typically used to build concurrent data structures in task-parallel runtime systems. To overcome these limitations, in a recent work we proposed XQueue, a novel lock-less concurrent queuing system with relaxed ordering semantics that is geared towards realizing scalability up to hundreds of concurrent threads. In this work, we extend XQueue and present X-OpenMP, a library for enabling extremely fine-grained parallelism on modern many-core systems with hundreds of cores. Work stealing is a popular choice for load balancing in task-based runtime systems as it efficiently distributes the load across worker threads; however, traditional approaches rely on synchronization primitives and thus work stealing can incur overheads. Here we implement a lock-less algorithm for work stealing for total-store order (TSO) memory architectures and evaluate the performance using micro and macro benchmarks. We compare the performance of X-OpenMP with native LLVM OpenMP, GNU OpenMP, OpenCilk and oneTBB implementations using task-based linear algebra routines from PLASMA numerical library, Strassen’s matrix multiplication from the BOTS Benchmark Suite, and the Unbalanced Tree Search benchmark. Applications parallelized using OpenMP can run without modification by simply linking against the X-OpenMP library. X-OpenMP achieves up to 40X speedup compared to GNU OpenMP, up to 2X speedup compared to the native LLVM OpenMP, up to 6X speedup compared to OpenCilk and up to 5X speedup compared to oneTBB implementations. The tasking overheads in X-OpenMP are reduced by 50% compared to the native LLVM OpenMP.

GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems

With the explosive growth of graph data, distributed graph processing becomes popular and many graph hardware accelerators use distributed frameworks. Graph partitioning is foundation in distributed graph processing. However, dynamic changes in graph make existing partitioning shifted from its optimized points and cause system performance degraded. Therefore, more efficient dynamic graph partition methods are needed. In this work, we propose GraphSER, a dynamic graph partition method for many-core systems. In order to improve the cross-node spatial locality and reduce the overhead of repartition, we propose a stream-based edge repartition, in which each computing node sequentially traverses its local edge list in parallel, then migrating edges based on distance and replica degree. GraphSER does not need costly searching and prioritizes nodes so it can avoid poor cross-node spatial locality. Our evaluation shows that compared to state-of-the-art edge repartition software methods, GraphSER has an average speedup 1.52x, with the maximum up to 2x. Compared to the previous many-core hardware repartition method, GraphSER performance has an average of 40% improvement, with the maximum to 117%.

A Two-Level Thermal Cycling-Aware Task Mapping Technique for Reliability Management in Manycore Systems

A Two-Level Thermal Cycling-Aware Task Mapping Technique for Reliability Management in Manycore Systems

On Task Mapping in Multi-chiplet Based Many-core Systems to Optimize Inter- and Intra-chiplet Communications

On Task Mapping in Multi-chiplet Based Many-core Systems to Optimize Inter- and Intra-chiplet Communications

Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems

Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems

A THREE-STEP TEACHING MODEL FOR MANY-CORE CACHE MEMORY DESIGN

The shift in processor design towards manycore architectures necessitates effective management of data in cache memories, posing challenges related to cache coherence and parallel computing. This paper proposes a three-step teaching model to meet the demand for designing cache memory for many-core systems. The steps include: 1) acquiring a comprehension of an open-source simulator like FM-SIM (Flexible Multicore Cache Simulator), 2) learning the process of collecting trace files using Pin Tools, and 3) designing and integrating a new cache memory and/or cache coherence protocol into FM-SIM to assess their efficacy. The proposed model has demonstrated its capability to enable students to make significant progress in exploring and researching modern cache memory design, particularly in the context of manycore architectures.

WrBench: Comparing Cache Architectures and Coherency Protocols on ARMv8 Many-Core Systems

wrBench: Comparing Cache Architectures and Coherency Protocols on ARMv8 Many-Core Systems

Design, threat analysis and countermeasures for cache replacement policy-affecting Hardware Trojans in the context of a many-core system

Hardware Trojans, which threaten system reliability and integrity, have emerged as a security threat to the IC industry. Hardware manufacturers acquire ICs from unreliable third parties to reduce time to market and cost. Integration of untrusted component(s) in the IC design cycle and malicious modification(s) of ICs in the design house or foundry is popularly known as the Hardware Trojan. Trojans are implanted within a system to cause system malfunction, destruction or leakage of confidential information. Here, we have designed stealthy Trojans that degrade system performance by intervening in the cache replacement policies of a system. One of the designed Trojans affects systems that use the least recently used (LRU) cache replacement policy and decreases the infected core’s HitRatio up to 7.09%. The other one affects systems that use least frequently used (LFU) cache replacement policy and decreases the HitRatio of the infected core up to 8.52%. The proposed mitigation technique can improve the infected core’s HitRatio up to 8.19%.

Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework

The complexity of manycore System-on-chips (SoCs) is growing faster than our ability to manage them to reduce the overall energy consumption. Further, as SoC design moves toward three-dimensional (3D) architectures, the core's power density increases leading to unacceptable high peak chip temperatures. In this article, we consider the optimization problem of dynamic power management (DPM) in manycore SoCs for an allowable performance penalty (say, 5%) and admissible peak chip temperature. We employ a machine learning– (ML) based DPM policy, which selects the voltage/frequency levels for different cluster of cores as a function of the application workload features such as core computation and inter-core traffic, and so on. We propose a novel learning-to-search (L2S) framework to automatically identify an optimized sequence of DPM decisions from a large combinatorial space for joint energy-thermal optimization for one or more given applications. The optimized DPM decisions are given to a supervised learning algorithm to train a DPM policy, which mimics the corresponding decision-making behavior. Our experiments on two different manycore architectures designed using wireless interconnect and monolithic 3D demonstrate that principles behind the L2S framework are applicable for more than one configuration. Moreover, L2S-based DPM policies achieve up to 30% energy-delay product savings and reduce the peak chip temperature by up to 17 °C compared to the state-of-the-art ML methods for an allowable performance overhead of only 5%.

Policy Gradient-Based Core Placement Optimization for Multichip Many-Core Systems.

As many deep neural network models become deeper and more complex, processing devices with stronger computing performance and communication capability are required. Following this trend, the dependence on multichip many-core systems that have high parallelism and reasonable transmission costs is on the rise. In this work, in order to improve routing performance of the system, such as routing runtime and power consumption, we propose a reinforcement learning (RL)- based core placement optimization approach, considering application constraints, such as deadlock caused by multicast paths. We leverage the capability of deep RL from indirect supervision as a direct nonlinear optimizer, and the parameters of the policy network are updated by proximal policy optimization. We treat the routing topology as a network graph, so we utilize a graph convolutional network to embed the features into the policy network. One step size environment is designed, so all cores are placed simultaneously. To handle large dimensional action space, we use continuous values matching with the number of cores as the output of the policy network and discretize them again for obtaining the new placement. For multichip system mapping, we developed a community detection algorithm. We use several datasets of multilayer perceptron and convolutional neural networks to evaluate our agent. We compare the optimal results obtained by our agent with other baselines under different multicast conditions. Our approach achieves a significant reduction of routing runtime, communication cost, and average traffic load, along with deadlock-free performance for inner chip data transmission. The traffic of interchip routing is also significantly reduced after integrating the community detection algorithm to our agent.

AMA: An Ageing Task Migration Aware for High-Performance Computing

The dark-silicon challenge poses a design problem for future many-core systems. As a result of this, several techniques have been introduced to improve the number of processing elements that can be powered on. One of the techniques employed by many is Task Migration. In this paper, an Ageing Task Migration Aware for High-Performance Computing (AMA) is proposed to improve the lifetime of nodes. The proposed method determines which clusters applications are mapped to and migrates high-demand tasks amongst nodes to improve the lifetime at every epoch. Experimental results show that the proposed method outperforms state-of-the-art techniques by more than 10%.

NoC-based hardware software co-design framework for dataflow thread management

Applications running in a large and complex manycore system can significantly benefit from adopting the dataflow model of computation. In a dataflow execution environment, a thread can run only if all its required inputs are available. While the potential benefits are large, it is not trivial to improve resource utilization and energy efficiency by focusing on dataflow thread execution models (i.e., the ways specifying how the threads adhering to a dataflow model of computation execute on a given compute/communication architecture). This paper proposes and implements a hardware-software co-design-based dataflow threads management framework. It works at the Network-on-Chip (NoC) level and consists of three stages. The first stage focuses on a fast and effective thread distribution policy. The next stage proposes an approach that adds reconfigurability to a 2D mesh NoC via customized instructions to manage the dataflow thread distribution. Finally, a 2D mesh and ring-based hybrid NoC is proposed for better scalability and higher performance. This work can be considered a primary reference framework from which extensions can be carried out.

COP: A Combinational Optimization Power Budgeting Method for Manycore Systems in Dark Silicon

Dark silicon is a phenomenon of under-utilization in today's manycore systems due to power and thermal limitations. In order to improve the performance of dark silicon systems, it is necessary to adopt dynamic power constraints for different core mapping decisions. However, existing power budgeting methods are generally over pessimistic, e.g. Thermal Safe Power (TSP), or over optimistic, e.g. Greedy based Dynamic Power (GDP). This paper proposes a practical power budgeting method, called Combinational Optimization Power (COP). Different from existing methods, which ignore some actual factors, such as communication overhead and lifetime reliability, COP formulates the power budgeting problem as a thermal-constrained combinational optimization power problem. For the steady-state case, COP achieves the target fusion of optimized temperature and communication energy consumption by applying task priority ranking and task-to-core mapping. For the transient case, COP uses the rainflow counting algorithm to construct the reliability framework based on the thermal cycling failure mechanism, and then establishes a linear time-invariant transient temperature model to obtain the core mapping selection and the corresponding dynamic power budget. Experimental results demonstrate that COP is capable of providing an optimized core mapping decision, which can maximize power budget while ensuring the system performance.

Detection of Thermal Covert Channel Attacks Based on Classification of Components of the Thermal Signal Features

In response to growing security challenges facing many-core systems imposed by thermal covert channel (TCC) attacks, a number of threshold-based detection methods have been proposed. In this paper, we show that these threshold-based detection methods are inadequate to detect TCCs that harness advanced signaling and specific modulation techniques. Since the frequency representation of a TCC signal is found to have multiple side lobes, this important feature shall be explored to enhance the TCC detection capability. To this end, we present a pattern-classification-based TCC detection method using an artificial neural network that is trained with a large volume of spectrum traces of TCC signals. After proper training, this classifier is applied at runtime to infer TCCs, should they exist. The proposed detection method is able to achieve a detection accuracy of 99%, even in the presence of the stealthiest TCCs ever discovered. Because of its low runtime overhead ( <inline-formula><tex-math notation="LaTeX">$&lt; 0.187\%$</tex-math></inline-formula> ) and low energy overhead ( <inline-formula><tex-math notation="LaTeX">$&lt; 0.072\%$</tex-math></inline-formula> ), this proposed detection method can be indispensable in fighting against TCC attacks in many-core systems. With such a high accuracy in detecting TCCs, powerful countermeasures, like the ones based on dynamic voltage and frequency scaling (DVFS), can be rightfully applied to neutralize any malicious core participating in a TCC attack.

On Allocation Algorithms for Manycore Systems With Network on Chip

Single-chip multicore processors and their network on chip interconnection mechanisms have received extensive interest since the early 2000s. The mesh topology is popular in networks on chip. A common issue in mesh is that it can result in high energy consumption and chip temperatures. It has been recently shown that mapping communicating tasks to neighboring cores can reduce communication delays and the associated power consumption and improve throughput. This paper evaluates the contiguous allocation strategy first fit and non-contiguous allocation strategies that attempt to achieve a degree of contiguity among the cores allocated to a job. One of the non-contiguous strategies is a new strategy, referred to as neighbor allocation strategy, which decomposes the job request so that it can be accommodated by free core submeshes and individual cores that have degree of contiguity. The results show that the relative merits of the policies depend on the job's communication pattern.

Modeling and Analysis of Thermal Covert Channel Attacks in Many-core Systems

In a many-core chip, thermal flux and thermal correlation among the cores can be explored to create a thermal covert channel (TCC). In this paper, we provide an analytical model to quickly determine the key TCC performance metrics, in terms of bit error rate (BER), signal to noise ratio (SNR), and channel capacity, without going through lengthy computer simulation and/or physical experiments that are normally needed in current TCC performance studies. According to our model, the TCC’s BER is proportional to the square root of the transmission frequency, which can be explored quantitatively to boost the TCC’s transmission efficiency by letting the TCC’s thermal signal be transmitted at a higher frequency. In addition, our proposed model also links the jamming noise and application of Dynamic Voltage Frequency Scaling (DVFS) to TCC’s BER performance, a feature that can be explored to design/optimize the countermeasures against the TCC attacks. The TCC performance predicted by the proposed theoretical model is found in a good agreement with that obtained from computer simulations, with an average error lower than 7%.

An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes

Increase in chip inactivity in the future threatens the performance of many-core systems and therefore, efficient techniques are required for continuous scaling of transistors. As of a result of this challenge, future proposed many-core system designs must consider the possibility of a 50% functioning chip per time as well maintaining performance. Fortunately, this 50% inactivity can be increased by managing the temperature of active nodes and the placement of the dark nodes to leverage a balance working chip whilst considering the lifetime of nodes. However, allocating dark nodes inefficiently can increase the temperature of the chip and increase the waiting time of applications. Consequently, due to stochastic application characteristics, a dynamic rescheduling technique is more desirable compared to fixed design mapping. In this paper, we propose an Ageing Before Temperature Electromigration-Aware, Negative Bias Temperature Instability (NBTI) & Time-dependent Dielectric Breakdown (TDDB) Neighbour Allocation (ABENA 2.0), a dynamic rescheduling management system which considers the ageing and temperature before mapping applications. ABENA also considers the location of active and dark nodes and migrate task based on the characteristics of the nodes. Our proposed algorithm employ Dynamic Voltage Frequency Scaling (DVFS) to reduce the Voltage and Frequency (VF) of the nodes. Results show that, our proposed methods improve the ageing of nodes compared to a conventional round-robin management system by 10% in temperature, and 10% ageing.

A Scalable Interconnection Scheme in Many-Core Systems

A Scalable Interconnection Scheme in Many-Core Systems