Circuit Manufacturing Research Articles

Application of Photolithography in Integrated Circuits

Integrated circuit (IC) manufacturing relies heavily on lithography, which drives device size reduction and performance improvement through precise pattern transfer. As the performance requirements of electronic devices continue to increase, lithography faces major challenges in terms of precision and efficiency. Currently, deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography technologies are mainstream, while technologies such as electron beam lithography (EBL) and directed self-assembly (DSA) are applied in specific high-precision fields. This paper reviews the current development status of lithography technology and analyzes its application in CMOS technology, 3D NAND flash memory, and high-performance computing components. The study also explores the main challenges facing photolithography, including technical bottlenecks, rising costs, and environmental impacts. In order to address these issues, the study emphasizes the importance of technological innovation and material improvement, especially in the development of new photoresists and mask materials and the promotion of environmentally friendly lithography technology. Therefore, it can be found that continued advances in lithography are essential to meet the changing needs of the semiconductor industry.

Reverse osmosis membrane fouling caused by typical surfactants in the integrated circuit industry: Fouling mechanism and control strategies.

In the integrated circuit manufacturing process, reverse osmosis (RO) membranes are widely used for wastewater reclamation. However, fouling by typical surfactants significantly reduces membrane efficiency and lifespan. This study investigates the fouling mechanisms of typical surfactants-cetyl trimethyl ammonium bromide (CTAB, cationic), sodium dodecyl sulfate (SDS, anionic), and polyoxyethylene octyl phenyl ether (TX, nonionic)-on RO membranes. Quartz crystal microbalance analysis results show that CTAB and TX exhibit significantly stronger adhesion to RO membranes than SDS. The order of adsorption mass on the membrane surface is CTAB > TX > SDS, with CTAB causing the most severe fouling. Molecular dynamics (MD) simulations indicate that unclustered CTAB molecules contribute to severe fouling by inserting into the membrane surface. As surfactant concentration increases, clustered CTAB is less likely to enter the membrane's surface layer. A comparison of oxidative technologies-continuous dual-wavelength ultraviolet (VUV/UV), intermittent VUV/UV, and intermittent VUV/UV with chlorine, ozone alone, chlorine alone, and ozone combined with chlorine (ozone/chlorine)- reveals that pre-treating surfactants with ozone/chlorine (simultaneous dosing at 10 mg/L each) before membrane filtration effectively controls fouling. After 30 min of treatment, 29 % of CTAB and 86 % of TX were degraded, respectively. Ozone/chlorine oxidation significantly alleviates membrane fouling, increasing the normalized steady-state permeate flux (Jpss) of CTAB and TX by 245 % and 151 %, respectively. The extended Derjaguin-Landau-Verwey-Overbeek theory calculations and MD simulations show that oxidation weakens the adhesion of CTAB and TX to RO membranes, reducing fouling. Ozone/chlorine treatment also effectively mitigates membrane fouling in actual wastewater from the electronics industry. Post-oxidation, the flux ratio (J/J0) increased from 0.28 to 0.52, resulting in a 116.7 % improvement in the Jpss. This study combines experimental data, theoretical calculations, and MD simulations, highlighting the significance of molecular clustering in surfactant-induced fouling before and after oxidation.

A framework for hardware trojan detection based on contrastive learning

With the rapid development of the semiconductor industry, Hardware Trojans (HT) as a kind of malicious function that can be implanted at will in all processes of integrated circuit design, manufacturing, and deployment have become a great threat in the field of hardware security. Side-channel analysis is widely used in the detection of HT due to its high efficiency, non-contact nature, and accuracy. In this paper, we propose a framework for HT detection based on contrastive learning using power consumption information in unsupervised or weakly supervised scenarios. First, the framework augments the data, such as creatively using a one-dimensional discrete chaotic mapping to disturb the data to achieve data augmentation to improve the generalization capabilities of the model. Second, the model representation is learned by comparing the similarities and differences between samples, freeing it from the dependence on labels. Finally, the detection of HT is accomplished more efficiently by categorizing the side information during circuit operation through the backbone network. Experiments on data from nine different public HTs show that the proposed method exhibits better generalization capabilities using the same network model within a comparative learning framework. The model trained on the dataset of small Trojan T100 has a detection efficiency advantage of up to 44% in detecting large Trojans, while the model trained on the dataset of large Trojan T2100 has a detection efficiency advantage of up to 10% in detecting small Trojans. The results in data imbalanced and noisy environments also show that the contrastive learning framework in this paper can better fulfill the requirements of detecting unknown HT in unsupervised or weakly supervised scenarios.

OPTIMIZATION PROBLEM FOR NUMBER OF LOGIC GATES NEEDED TO IMPLEMENT MULTIPLE BOOLEAN FUNCTIONS USING DECODER

Abstract. Background. Computer circuits enable almost every piece of electronics to function. An opportunity for their optimization was found in one of the ways to implement a circuit, which involves a decoder. Decoders are basic circuit components whose behavior makes it easy to implement multiple Boolean functions. Functions are just rules by which informational signals are being processed in the circuit. To implement a function Logic gatEs (LEs) are used. LEs group multiple input signals and process them using binary logic operators like AND or NOR. Purpose. Develop a computer program that, based on provided functions, will find a solution associated with approximately minimal number of logic gates. Relevance. Prevalence of circuits increases the value of small optimizations, since any improvement gets multiplied by millions of circuits produced. Optimization at the logic level is being explored, which will retain value regardless of the physical properties of the circuit. Additionally, the theory of optimizing LE usage for circuits built on decoders is examined, which will alleviate future research. Methods. Development of the theory arose from an understanding that input signals can be grouped using LEs consciously. This way, LE outputs can be used in more than one function, which results in reduction of total number of LEs. It becomes evident that the problem can be restated in terms of sets. Similarity to known NP-hard problems emerges, which prompts usage of existing solution approaches. Among them, the greedy algorithm is chosen for its simplicity in program implementation. The connection between the problem and digital circuitry is weakened by the introduction of special evaluation functions that work with sets. So, the problem is reduced to several mathematical rules, which then are used as the appropriate parts of the greedy algorithm. Development of knowledge necessary to create the target program is thus concluded. Results. The target program is successfully implemented and can be seen in full at https://github.com/Gleb-05/MakeFuncForDC. A test is conducted on 1000 sets of four pseudorandom eight-term functions. It is estimated that the implementations proposed by the program require on average 0.75 of the initial number of LEs. The average running time is estimated at 2 milliseconds. In contrast, brute-force search for the same problem is theorized to run for years. Conclusions. A working program that finds an almost optimal solution is successfully created and tested. Its performance makes it potentially useful in the industrial scale of circuit manufacturing. Since the program essentially offers workload management, its possible applications go beyond the domain of digital electronics. Additionally, the theory of optimizing the use of LEs is presented for the first time. It can be used as the basis for future research on the implementation of multiple Boolean functions using decoder.

Inductance and penetration depth measurements of polycrystalline NbN films for all-NbN single flux quantum circuits

Abstract In this paper, we report on a systematic study of the inductance and magnetic field penetration depth (λ) of polycrystalline NbN superconducting thin films. By employing a four-metal-layer fabrication process specifically designed for all-NbN single-flux-quantum circuits, we constructed a superconducting quantum interference device loop composed of two parallel NbN SNS junctions, NbN microstrips, and NbN ground planes for precise inductance measurement. At 4.2 K, as the linewidth increases from 1 μm to 30 μm, the inductance per unit length (L u) of NbN microstrips significantly decreases, for example, the L u of 250 nm thick NbN microstrips drops from 0.907 pH/μm to 0.047 pH/μm. Compared to Nb, the L u of polycrystalline NbN microstrips is approximately two to three times that of Nb, offering an advantage for manufacturing smaller superconducting inductors. Furthermore, we conducted simulation analysis using InductEx software to extract the λ of NbN films of varying thicknesses. The results indicate that as the film thickness increased from 45 nm to 600 nm, λ initially decreased sharply and then stabilized, with values ranging from 430 nm to 323 nm. Notably, once the film thickness exceeded 200 nm, λ remained essentially constant, even at a temperature of 10 K, where it showed good stability, albeit with a slight increase (about 50 nm) compared to 4.2 K. This dependence of λ on thickness is reasonably explained by considering the effects of NbN film thickness on the superconducting critical temperature and residual resistivity. These research findings not only deepen our understanding of the characteristics of superconducting films but also lay a solid foundation for the future design and manufacture of more compact superconducting circuits at the higher temperature of 10 K.

Virtual X-ray critical dimension metrology via Monte Carlo simulation.

X-ray critical dimension (XCD) metrology is a highly promising technique for achieving sub-nanometer precision in critical dimension measurements at advanced nodes of integrated circuit manufacturing. Compared to XCD experiments utilizing synchrotron radiation sources, those employing compact X-ray sources encounter challenges like extended testing time and increased uncertainty. To evaluate the influence of experimental conditions on measurement results, we developed an ab initio virtual X-ray critical dimension metrology via a Monte Carlo simulation (MC-VXCD). Through calibrating the system parameters of the MC-VXCD to a home-built compact XCD instrument, we achieved excellent consistency between virtual and actual measurement results. The virtual instrument effectively estimated measurement errors stemming from the reduced exposure time, which significantly influences the measurement accuracy and throughput. Furthermore, through the MC-VXCD, we establish the connection between the application scenarios of the XCD metrology and the geometry of XCD instruments, offering a versatile platform for the system design, experimental configuration optimization, data analysis, etc., in XCD metrology.

Plasmonic lithography fast imaging model based on least square fitting for periodic patterns

As a new and alternative lithography technology, plasmonic lithography can break through the diffraction limit of traditional lithography by exciting the surface plasmon polaritons to make the evanescent wave at the mask participate in imaging. Plasmonic lithography is capable of fabricating deep subwavelength structures for nanophotonics, metasurfaces, and various other applications, and it is expected to be applied to integrated circuit manufacturing. The photoresist aerial image distribution of different mask patterns can be calculated by establishing an imaging model, which is the basis for understanding and further optimizing imaging. Based on the idea of machine learning and least square fitting, a fast imaging model for plasmonic lithography is established, including a one-dimensional line/space periodic pattern and a two-dimensional square hole pattern, which can be used as a supplement to the previous model developed by Ding et al. [Opt. Express 31, 192 (2023)OPEXFF1094-408710.1364/OE.476825]. Compared with the rigorous numerical method, the fast imaging model can greatly improve the calculation speed with high accuracy. Under the same hardware conditions, the calculation speed of the 1D fast imaging model is improved by two orders of magnitude, and the 2D fast imaging model is improved by about 25 times, which creates conditions for the development of computational lithography technology.

Quasi-visualizable detection of deep sub-wavelength defects in patterned wafers by breaking the optical form birefringence

Abstract In integrated circuit (IC) manufacturing, fast, nondestructive, and precise detection of defects in patterned wafers, realized by bright-field microscopy, is one of the critical factors for ensuring the final performance and yields of chips. With the critical dimensions of IC nanostructures continuing to shrink, directly imaging or classifying deep-subwavelength defects by bright-field microscopy is challenging due to the well-known diffraction barrier, the weak scattering effect, and the faint correlation between the scattering cross-section and the defect morphology. Herein, we propose an optical far-field inspection method based on the form-birefringence scattering imaging of the defective nanostructure, which can identify and classify various defects without requiring optical super-resolution. The technique is built upon the principle of breaking the optical form birefringence of the original periodic nanostructures by the defect perturbation under the anisotropic illumination modes, such as the orthogonally polarized plane waves, then combined with the high-order difference of far-field images. We validated the feasibility and effectiveness of the proposed method in detecting deep subwavelength defects through rigid vector imaging modeling and optical detection experiments of various defective nanostructures based on polarization microscopy. On this basis, an intelligent classification algorithm for typical patterned defects based on a dual-channel AlexNet neural network has been proposed, stabilizing the classification accuracy of λ/16-sized defects with highly similar features at more than 90%. The strong classification capability of the two-channel network on typical patterned defects can be attributed to the high-order difference image and its transverse gradient being used as the network’s input, which highlights the polarization modulation difference between different patterned defects more significantly than conventional bright-field microscopy results. This work will provide a new but easy-to-operate method for detecting and classifying deep-subwavelength defects in patterned wafers or photomasks, which thus endows current online inspection equipment with more missions in advanced IC manufacturing.

OPTIMIZATION PROBLEM FOR NUMBER OF LOGIC GATES NEEDED TO IMPLEMENT MULTIPLE BOOLEAN FUNCTIONS USING DECODER

Abstract. Background. Computer circuits enable almost every piece of electronics to function. An opportunity for their optimization was found in one of the ways to implement a circuit, which involves a decoder. Decoders are basic circuit components whose behavior makes it easy to implement multiple Boolean functions. Functions are just rules by which informational signals are being processed in the circuit. To implement a function Logic gatEs (LEs) are used. LEs group multiple input signals and process them using binary logic operators like AND or NOR. Purpose. Develop a computer program that, based on provided functions, will find a solution associated with approximately minimal number of logic gates. Relevance. Prevalence of circuits increases the value of small optimizations, since any improvement gets multiplied by millions of circuits produced. Optimization at the logic level is being explored, which will retain value regardless of the physical properties of the circuit. Additionally, the theory of optimizing LE usage for circuits built on decoders is examined, which will alleviate future research. Methods. Development of the theory arose from an understanding that input signals can be grouped using LEs consciously. This way, LE outputs can be used in more than one function, which results in reduction of total number of LEs. It becomes evident that the problem can be restated in terms of sets. Similarity to known NP-hard problems emerges, which prompts usage of existing solution approaches. Among them, the greedy algorithm is chosen for its simplicity in program implementation. The connection between the problem and digital circuitry is weakened by the introduction of special evaluation functions that work with sets. So, the problem is reduced to several mathematical rules, which then are used as the appropriate parts of the greedy algorithm. Development of knowledge necessary to create the target program is thus concluded. Results. The target program is successfully implemented and can be seen in full at https://github.com/Gleb-05/MakeFuncForDC. A test is conducted on 1000 sets of four pseudorandom eight-term functions. It is estimated that the implementations proposed by the program require on average 0.75 of the initial number of LEs. The average running time is estimated at 2 milliseconds. In contrast, brute-force search for the same problem is theorized to run for years. Conclusions. A working program that finds an almost optimal solution is successfully created and tested. Its performance makes it potentially useful in the industrial scale of circuit manufacturing. Since the program essentially offers workload management, its possible applications go beyond the domain of digital electronics. Additionally, the theory of optimizing the use of LEs is presented for the first time. It can be used as the basis for future research on the implementation of multiple Boolean functions using decoder.

Piezoelectric Shunt Damping for a Planar Motor Application under Cryogenic Conditions

For several decades, Moore’s law has driven the semiconductor industry, with computational power and production costs as the main drivers. Such drivers have enabled several technological innovations in the mechatronics and dynamics architecture of photolithography machines, used for semiconductor circuits manufacturing. Among current investigations, the use of superconductive magnets would enable higher accelerating stages and, thus, higher throughput and lower manufacturing costs. However, this involves a complex magnet structure that needs to operate at cryogenic temperatures and mechanical resonances at relatively low frequencies as a result of the thermal architecture of the system. The damping options are also limited due to the very low temperature. This paper explores the use of shunted piezoelectric transducers for damping the internal modes of the magnet mass. A classical resistive and inductive RL shunt is considered. The study was conducted both numerically and experimentally on a demonstrator of a superconductive magnet plate concept, where piezoelectric transducers are incorporated to support the superconducting coils. The study demonstrates the effectiveness of piezoelectric shunts as a damping solution at very low temperatures, with limited impact of the temperature variation on the performance.

Enhanced particle removal ability of two representative nonionic surfactants: A reasonable interpretation based on DFT and coarse-grained molecular dynamics methods

Cleaning of copper surfaces after chemical mechanical polishing is indispensable for removing particle residues, which is a critical step in integrated circuits manufacturing. This paper introduces two nonionic surfactants, coconut oil diethanolamine (CDEA) and fatty alcohol polyoxyethylene ether (AEO-9), into a basic alkaline cleaning solution comprising tetraethyl ammonium hydroxide and lysine to investigate their abilities to enhance particle removal performance. Cleaning performance was measured with scanning electron microscopy, which showed that the two surfactants achieved excellent particle removal efficiency (above 95 %), with CDEA performing slightly better in all tested concentrations. Concerning critical micelle concentration, surface tension tests showed that CDEA (at 1500 ppm) had superior wettability and dispersive capacity compared with AEO-9 (at 2000 ppm) and could prevent particle redeposition more effectively. Using density functional theory, CDEA was found to have more polar groups to form hydrogen bonds with the hydrophilic surface of colloidal silica particles or bond with the copper substrate, explaining CDEA’s ability to lower the surface tension of the cleaning solution and improve the zeta potential between particles and the copper substrate. Finally, based on the Martini forcefield, simulations of coarse-grained molecular dynamics provided valuable theoretical insights into the different dispersion abilities of the two nonionic surfactants that CDEA had a more significant diffusion coefficient (0.073 Å2/ps) and was able to form micelles more efficiently in solution compared with that of AEO-9 (0.066 Å2/ps).

Development Status of Key Technologies for Optoelectronic Integrated Circuit Manufacturing

Optoelectronic integrated circuit (OEIC) technology has attracted considerable research attention. Studies have achieved numerous breakthroughs in the basic scientific problems, key technologies, demonstration applications, and industrial promotions of OEIC. This study details the technical process, development status, existing problems, and future research trends of the design, manufacturing, and packaging of OEIC to provide a systematic summary of OEIC technology.

Texture Evolution of High-purity Tantalum during 90°Clock Rolling

Abstract When fabricating high-purity tantalum targets for the sputtering procedure of integrated circuit manufacturing, a through-thickness texture gradient can form in the rolled tantalum (Ta) plate. This texture gradient hinders the target sputtering performance, reducing chip reliability. This study investigated the texture evolution during the 90°clock rolling through experimental and simulation methods. Balancing the plane strain deformation with the surface shear strain deformation during fabrication and limiting the total rolling reduction to no more than 85% can weaken the through-thickness texture gradient in the Ta plate. A crystal plasticity finite element method (CPFEM) model was developed to simulate the 90°clock rolling procedure in the ABAQUS/Explicit software. The simulation and the experimental results are in agreement, with slight differences in texture type and intensity due to tantalum’s complex slip behaviors.

Iterative printing of bulk metal and polymer for additive manufacturing of multi-layer electronic circuits

In pursuing advancing additive manufacturing (AM) techniques for 3D objects, this study combines AM techniques for bulk metal and polymer on a single platform for one-stop printing of multilayer 3D electronic circuits with two novel aspects. The first innovation involves the embedded integration of electronic circuits by printing low-resistance electrical traces from bulk metal into polymer channels. Cross-section grinding results reveal (92 ± 5)% occupancy of electrically conductive traces in polymer channels despite the different thermal properties of the two materials. The second aspect encompasses the possibility of printing vertical bulk metal vias up to 10 mm in height with the potential for expansion, interconnecting electrically conductive traces embedded in different layers of the 3D object. The work provides comprehensive 3D printing design guidelines for successfully integrating fully embedded electrically conductive traces and the interconnecting vertical bulk metal vias. A smooth and continuous workflow is also introduced, enabling a single-run print of functional multilayer embedded 3D electronics. The design rules and the workflow facilitate the iterative printing of two distinct materials, each defined by unique printing temperatures and techniques. Observations indicate that conductive traces using molten metal microdroplets show a 12-fold reduction in resistance compared to nanoparticle ink-based methods, meaning this technique greatly complements multi-material additive manufacturing (MM-AM). The work presents insights into the behavior of molten metal microdroplets on a polymer substrate when printed through the MM-AM process. It explores their characteristics in two scenarios: When they are deposited side-by-side to form conductive traces and when they are deposited out-of-plane to create vertical bulk metal vias. The innovative application of MM-AM to produce multilayer embedded 3D electronics with bulk metal and polymer demonstrates significant potential for realizing the fabrication of free-form 3D electronics.

Achieving ultralow contact resistance and reducing residual hydrogen by surface doping

Indium gallium zinc oxide (IGZO)-based materials and devices hold a significant position in integrated circuit manufacturing industries, yet challenges persist in controlling residual hydrogen and managing high source/drain contact resistance. Our proposed hypothesis not only targets the control of residual hydrogen through out-diffusion but also offers an opportunity for surface doping of IGZO, promising a substantial reduction in contact resistance. Interestingly, a 30 s hydrogen plasma deposition resulted in a lower hydrogen concentration compared to the residual hydrogen in IGZO, leading to increased carrier density at the interface. The higher carrier density, coupled with metallization-induced band bending at the interface, significantly lowers the Schottky barrier height and density of states, thereby facilitating sophisticated electron transport between molybdenum and IGZO. To the best of our knowledge, this study represents the first substantial reduction in residual hydrogen from IGZO films (initially deposited at 1020 cm−3, reduced to 1019 cm−3), while achieving ultralow specific contact resistivity (2.47 × 10-9 Ω•cm2) and sheet resistance (177.67 Ω/□). Our hypothesis introduces a novel strategy to reduce contact resistance in electronic devices.

Surface Orthogonal Patterning and Bidirectional Self-Assembly of Nanoparticles Tethered by V-Shaped Diblock Copolymers.

We investigated the surface orthogonal patterning and bidirectional self-assembly of binary hairy nanoparticles (NPs) constructed by uniformly tethering a single NP with multiple V-shaped AB diblock copolymers using Brownian dynamics simulations in a poor solvent. At low concentration, the chain collapse and microphase separation of binary polymer brushes can lead to the patterning of the NP surface into A- and B-type orthogonal patches with various numbers of domains (valency), n = 1-6, that adopt spherical, linear, triangular, tetrahedral, square pyramidal, and pentagonal pyramidal configurations. There is a linear relationship between the valency and the average ratio of NP diameter to the polymers' unperturbed root-mean-square end-to-end distance for the corresponding valency. The linear slope depends on the grafting density and is independent of the interaction parameters between polymers. At high concentration, the orthogonal patch NPs serve as building blocks and exhibit directional attractions by overlapping the same type of domains, resulting in self-assembly into a series of fascinating architectures depending on the valency and polymer length. Notably, the 2-valent orthogonal patch NPs have the bidirectional bonding ability to form the two-dimensional (2D) square NP arrays by two distinct pathways. Simultaneously patching A and B blocks enables the one-step formation of 2D square arrays via bidirectional growth, whereas step-by-step patching causes the directional formation of 1D chains followed by 2D square arrays. Moreover, the gap between NPs in the 2D square arrays is related to the polymer length but independent of the NP diameter. These 2D square NP arrays are of significant value in practical applications such as integrated circuit manufacturing and nanotechnology.

Hybrid additive-subtractive manufacturing of high-density copper-based flexible transparent circuits based on side-etch process

High-density flexible transparent circuits (FTCs) are widely used in 5G/6G flexible transparent antennas, wearable devices, flexible transparent electronics and other fields. However, the rapid iteration and upgrading of electronic circuits present significant challenges to the manufacturing of both high-density and high-precision circuits (especially copper-based circuits) at room temperature, in an efficient and flexible manner. Here, we employ the side-etching phenomenon, which is typically avoided, to propose a novel method for hybrid additive-subtractive fabricating high-density copper-based FTCs that combines electric field-driven (EFD) microjet printing and wet etching technology. Firstly, the customized photoresist mask was flexibly printed on the copper-clad flexible substrate by EFD microjet printing, and then the copper circuit with less than the mask resolution was obtained by the side etching process of the wet etching process. By optimizing process parameters and precisely controlling the speed of the side etching stage during the etching process, the manufacturing of high-precision copper-based FTCs with a minimum line width of 2.4 μm and a minimum pitch of 4 μm was achieved. The typical sample is manufactured with a resistivity of 4 × 10−6 Ω·cm, a sheet resistance of 3.58 Ω/sq at a transmittance of up to 87.65 % (including the substrate), and it exhibits excellent mechanical stability. The prepared high-density flexible transparent interdigital electrode has excellent sensitivity, and can detect the concentration change of dilute H2SO4 solution at a minimum of 1 nmol/L at a frequency of 100–10,000 Hz. This method provides a new solution for the fabrication of copper-based FTCs at room temperature with high efficiency and low cost, and shows a good prospect for industrial application.

The corrosion inhibition performance and mechanism of α-benzoin oxime on copper: A comprehensive study of experiments and DFT calculations

Copper corrosion poses a significant challenge to process stability and chip quality in the field of integrated circuit manufacturing. This study comprehensively explored the corrosion inhibition performance of α-benzoin oxime (bzoxH2) on copper, by employing a combination of experimental methods and computational chemistry. First, after the addition of 0.1 mM bzoxH2, the static etching rate and surface roughness of copper were decreased to 7 Å·min−1 and 1.36 nm, respectively, which indicated that bzoxH2 could reduce the corrosion rate of copper and improve its surface quality. Subsequently, electrochemical behavior analysis showed that the addition of 0.1 mM bzoxH2 resulted in an increase in open circuit potential to 0.185 V, a decrease in corrosion current density to 2.33 µA·cm−2, an increase in polarization resistance to 10589 Ω·cm2, and a high corrosion inhibition efficiency of 96.88 %, suggesting that bzoxH2 significantly enhances the corrosion resistance of copper. Furthermore, studies based on adsorption isotherm models indicated that the adsorption behavior of bzoxH2 on the copper surface formed a dense passivation film through the combination of physical and chemical adsorption mechanisms. This effectively enhanced the corrosion resistance of copper and provided robust protection against corrosion. Finally, the use of X-ray photoelectron spectroscopy technology, along with an in-depth exploration of the geometric structure and chemical reactivity of the bzoxH2 molecule, revealed its complex interaction with specific active sites on the copper surface. These findings provided valuable theoretical insights, along with practical guidance for the development of metal corrosion inhibitors.

Theoretical Understanding of Electromigration-Related Surface Diffusion and Current-Induced Force in Ag-Pd Systems.

Electromigration, as a common reason for interconnect failure, is becoming increasingly important in the ongoing decrease in the integrated circuit manufacturing process. A study is being carried out utilizing the ab initio calculational method to gain a deeper understanding of electromigration, with a focus on the atom diffusion process in the Ag-Pd alloy system, a commonly used interconnect material. We begin by establishing that the primary mechanism of diffusion is step-edge diffusion on the (111) surface. Following this, we examine the current-induced force exerted on the migrating Ag atom. The Pd substitutional defect reveals an effect that increases the energy barrier of diffusion and decreases the current-induced force that powers the directional migration.

Mask structure optimization for beyond EUV lithography.

Beyond extreme ultraviolet (BEUV) lithography with a 6 × nm wavelength is regarded as a future technique to continue the pattern shirking in integrated circuit (IC) manufacturing. This work proposes an optimization method for the mask structure to improve the imaging quality of BEUV lithography. Firstly, the structure of mask multilayers is optimized to maximize its reflection coefficient. Then, a mask diffraction near-field (DNF) model is established based on the Born series algorithm, and the aerial image of BEUV lithography system can be further calculated. Additionally, the mask absorber structure is inversely designed using the particle swarm optimization (PSO) algorithm. Simulation results show a significant improvement of the BEUV lithography imaging obtained by the proposed optimization methods. The proposed workflow can also be expanded to areas of EUV and soft x ray imaging.