Mantissa Multiplication Research Articles

An energy‐efficient floating‐point compute SRAM with pipelined in‐memory bit‐parallel exponent and bitwise mantissa processing

AbstractThe promise of compute‐in‐memory (CIM) for energy‐efficient deep neural network (DNN) tasks has been demonstrated. However, most previous CIM works typically focus on low‐precision DNN computing. To enable high‐precision DNN computing, this work presents a novel SRAM‐CIM design that fully supports half‐precision floating‐point (FP16) MAC operations. To maximize the energy efficiency, an efficient in‐memory bit‐parallel approach for conducting exponent operations and the bitwise in‐memory booth encoder for reducing mantissa multiplication latency are proposed. Moreover, by enabling the pipeline of exponent and mantissa processing, the hardware utilization is improved with high throughput achieved. The proposed design is analyzed in 40 nm CMOS technology. The evaluation shows that the SRAM‐CIM achieves a frequency of 714 MHz and a peak energy efficiency of 1.53 TFLOPS/W.

Design of Power Efficient Posit Multiplier using Compressor Based Adder

Abstract: Posit number system has been used in many applications, especially the deep learning. Because of how well its nonuniform number distribution aligns with deep learning's data distribution, deep learning's training process can be sped up. The hardware multiplier is typically built with the widest mantissa bit-width available due to the flexibility of posit numbers' bitwidth. Such multiplier designs consume a lot of power since the mantissa bit-width is not necessarily the maximum value. This is especially true when the mantissa bit-width is tiny. The mantissa multiplier is still built to have the widest bit-width feasible, but it is broken into numerous smaller multipliers. At run-time, just the necessary tiny multipliers are turned on. The regime bitwidth, which can be used to determine the mantissa bit-width, controls those smaller multipliers. This design technique is applied to 8-bit, 16-bit, and 32-bit posit formats.

All-Digital Computing-in-Memory Macro Supporting FP64-Based Fused Multiply-Add Operation

Recently, frequent data movement between computing units and memory during floating-point arithmetic has become a major problem for scientific computing. Computing-in-memory (CIM) is a novel computing paradigm that merges computing logic into memory, which can address the data movement problem with excellent power efficiency. However, the previous CIM paradigm failed to support double-precision floating-point format (FP64) due to its computing complexity. This paper presents a novel all-digital CIM macro-DCIM-FF to complete FP64 based fused multiply-add (FMA) operation for the first time. With 16 sub-CIM cells integrating digital multipliers to complete mantissa multiplication, DCIM-FF is able to provide correct rounded implementations for normalized/denormalized inputs in round-to-nearest-even mode and round-to-zero mode, respectively. To evaluate our design, we synthesized and tested the DCIM-FF macro in 55-nm CMOS technology. With a minimum power efficiency of 0.12 mW and a maximum computing efficiency of 26.9 TOPS/W, we successfully demonstrated that DCIM-FF can run the FP64-based FMA operation without error. Compared to related works, the proposed DCIM-FF macro shows significant power efficiency improvement and less area overhead based on CIM technology. This work paves a novel pathway for high-performance implementation of an FP64-based matrix-vector multiplication (MVM) operation, which is essential for hyperscale scientific computing.

An area-delay efficient single-precision floating-point multiplier for VLSI systems

The floating-point multiplier (FPM) is the most commonly used component in various image and signal processing applications. An area-delay efficient FPM design could be helpful for the development of high-performance VLSI computing systems. Therefore, this paper presents the analysis of single-precision FPM to find the possibilities for the reduction in delay and area. From the analysis, it is found that the delay of FPM depends on the delay of mantissa multiplication and exponent normalization units. Based on the above observations, in this paper, the delay and area efficient mantissa multiplication and exponent addition-cum-normalization units are proposed. Further, using these components, the single-precision FPM structure is proposed. Synthesis results show that the proposed FPM design offers a saving of 15.3% in delay and 10.8% in area compared to the best available existing FPM design. Besides, the proposed FPM consumes 13.0% less power-delay-product and involves 24.4% less area-delay-product in comparison to the best available existing design. Finally, effectiveness of the proposed single precision floating-point multiplier is presented in Gaussian smoothing filter of the image processing application.

CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs

The use of artificial intelligence (AI) in sensor analytics is entering a new era based on the use of ubiquitous embedded connected devices. This transformation requires the adoption of design techniques that reconcile accurate results with sustainable system architectures. As such, improving the efficiency of AI hardware engines as well as backward compatibility must be considered. In this paper, we present the Hybrid-Float6 (HF6) quantization and its dedicated hardware design. We propose an optimized multiply-accumulate (MAC) hardware by reducing the mantissa multiplication to a multiplexor-adder operation. We exploit the intrinsic error tolerance of neural networks to further reduce the hardware design with approximation. To preserve model accuracy, we present a quantization-aware training (QAT) method, which in some cases improves accuracy. We demonstrate this concept in 2D convolution layers. We present a lightweight tensor processor (TP) implementing a pipelined vector dot-product. For compatibility and portability, the 6-bit floating-point (FP) is wrapped in the standard FP format, which is automatically extracted by the proposed hardware. The hardware/software architecture is compatible with TensorFlow (TF) Lite. We evaluate the applicability of our approach with a CNN-regression model for anomaly localization in a structural health monitoring (SHM) application based on acoustic emission (AE). The embedded hardware/software framework is demonstrated on XC7Z007S as the smallest Zynq-7000 SoC. The proposed implementation achieves a peak power efficiency and run-time acceleration of 5.7 GFLOPS/s/W and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$48.3\times $ </tex-math></inline-formula> , respectively.

Approximate Floating-Point Multiplier based on Static Segmentation

In this paper a novel low-power approximate floating-point multiplier is presented. Since the mantissa computation is responsible for the largest part of the power consumption, we apply a novel approximation technique to mantissa multiplication, based on static segmentation. In our approach, the inputs of the mantissa multiplier are properly segmented so that a small inner multiplier can be used to calculate the output, with beneficial impact on power and area. To further improve performance, we introduce a novel segmentation-and-truncation approach which allows us to eliminate the shifter normally present at the output of the segmented multiplier. In addition, a simple compensation term for reducing approximation error is employed. The accuracy of the circuit can be tailored at the design time, by acting on a single parameter. The proposed approximate floating-point multiplier is compared with the state-of-the-art, showing good performance in terms of both precision and hardware saving. For single-precision floating-point format, the obtained NMED is in the range 10−5–7 × 10−7, while MRED is in the range 3 × 10−3–1.7 × 10−4. Synthesis results in 28 nm CMOS show area and power saving of up to 82% and 85%, respectively, compared to the exact floating-point multiplier. Image processing applications confirm the expectations, with results very close to the exact case.

Logarithm-approximate floating-point multiplier

Approximate computing is a useful approach to save power and increase performance by trading Energy and accuracy. This paper proposes an efficient inexact floating-point (FP) multiplier using the idea of a semi-logarithm multiplier. In the proposed approximate FP multiplier, instead of the traditional mantissa multiplier, an approximate adder is used. The results show that the power consumption and delay of the proposed approximate FP multiplier have been decreased by 97% and 53% compared with the IEEE-754 single-precision exact FP multiplier. In addition, the proposed approximate FP multiplier provides an improvement of 81% in terms of area. Compared to the logarithm-approximate FP multiplier, the proposed inexact FP multiplier has 81%, 34%, and 34% savings in power, area, and delay parameters, respectively. High dynamic range (HDR) images are processed using the proposed approximate FP multiplier in smoothing and sharpening applications to show the quality of the proposed FP multiplier in image processing.

Quantum-dot cellular automata based design of multifunction binary right shifter circuit

This article explores the basic design methodology of a 4-bit binary right shifter circuit and its implementation based on a QCA nano-device. The right shifter circuit can shift a single bit of an input message. The proposed shifter has been reorganized to function as a logical, arithmetic, and circular right shifter. Single-layer wire intersection has been utilized to give the most straightforward execution of the plans. These designs are helpful in floating-point handling frameworks, incredibly exceptionally valuable for the mantissa multiplication procedure. The design correctness is confirmed by contrasting hypothetical qualities and relating simulation results. The shifter consumes 435 QCA cells, 0.89µm2 area with a latency of 1.75, and a circuit cost of 264.06. The design is compared with other shifters in terms of design complexities. The design has 0.628eV energy consumption at tunneling energy level 1.0Ek (kink energy). But it consumes only 0.190eV energy to perform multifunction shifting operations.

Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers

Approximate computing has emerged as a promising design alternative for delivering power-efficient systems and circuits by exploiting the inherent error resiliency of numerous applications. The current article aims to tackle the increased hardware cost of floating-point multiplication units, which prohibits their usage in embedded computing. We introduce AFMU (Approximate Floating-point MUltiplier), an area/power-efficient family of multipliers, which apply two approximation techniques in the resource-hungry mantissa multiplication and can be seamlessly extended to support dynamic configuration of the approximation levels via gating signals. AFMU offers large accuracy configuration margins, provides negligible logic overhead for dynamic configuration, and detects unexpected results that may arise due to the approximations. Our evaluation shows that AFMU delivers energy gains in the range 3.6%–53.5% for half-precision and 37.2%–82.4% for single-precision, in exchange for mean relative error around 0.05%–3.33% and 0.01%–2.20%, respectively. In comparison with state-of-the-art multipliers, AFMU exhibits up to 4–6× smaller error on average while delivering more energy-efficient computing. The evaluation in image processing shows that AFMU provides sufficient quality of service, i.e., more than 50 db PSNR and near 1 SSIM values, and up to 57.4% power reduction. When used in floating-point CNNs, the accuracy loss is small (or zero), i.e., up to 5.4% for MNIST and CIFAR-10, in exchange for up to 63.8% power gain.

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating-point multiplication is an important component. The dynamic range of numbers represented by floating-point arithmetic is very large compared with that of fixed-point numbers of the same bit width. A mantissa similarity investigator (MSI)–interfaced multi-precision binary multiplier architecture is developed and can be used in data-intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single-, double-, quadruple- and octuple-precision modes for mantissa multiplication according to the IEEE 754 standard for floating-point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field-programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator.

Improvised hierarchy of floating point multiplication using 5:3 compressor

ABSTRACT The main objective is to develop floating-point multiplication (FPM) using 5:3 compressor based Vedic multiplier (VM), Karatsuba algorithm (KA) and canonical signed digit (CSD) algorithm to overcome the drawbacks presented in conventional compressor based FPM. In this scenario, an attempt is made to enhance the performance of FPM using three efficient algorithms. Finally, the performance analysis in terms of area, delay and power dissipation of using VM, KA and CSD with 5:3 compressor are examined and compared. The designs f00which are involved in mantissa multiplication are coded in Verilog HDL and implemented using Xilinx Vivado. It is clearly convinced from the 5:3 compressor based CSD that it provides better performance than other two algorithms by achieving acceptable area and delay. Single precision floating point multiplication (SPFPM) using Vedic with 5:3 compressor requires 29% Look Up Table (LUT) area and 30% slice area improvement in comparing with KA. In case of delay, KA gives 35% improvement compared to vedic based SPFPM. For CSD algorithm based SPFPM requires 46% improvement in LUTs area and 49% improvement in Slice area compared to KA based SPFPM.

Design of Power Efficient Posit Multiplier

Posit number system has been used as an alternative to IEEE floating-point number system in many applications, especially the recent popular deep learning. Its non-uniformed number distribution fits well with the data distribution of deep learning and thus can speedup the training process of deep learning. Among all the related arithmetic operations, multiplication is one of the most frequent operations used in applications. However, due to the bit-width flexibility nature of posit numbers, the hardware multiplier is usually designed with the maximum possible mantissa bit-width. As the mantissa bit-width is not always the maximum value, such multiplier design leads to a high power consumption especially when the mantissa bit-width is small. In this brief, a power efficient posit multiplier architecture is proposed. The mantissa multiplier is still designed for the maximum possible bit-width, however, the whole multiplier is divided into multiple smaller multipliers. Only the required small multipliers are enabled at run-time. Those smaller multipliers are controlled by the regime bit-width which can be used to determine the mantissa bit-width. This design technique is applied to 8-bit, 16-bit, and 32-bit posit formats in this brief and an average of 16% power reduction can be achieved with negligible area and timing overhead.

Implementation of 64 Bit Complex Floating-Point Multiplier on FPGA using Vedic Mathematics Sutra- Urdhva Tiryagbhyam

Multipliers play crucial role in present days in the area of digital signal processing and in communication systems applications. The entire system performance depends on speed area and power of the multipliers. In our paper, we developed a 64x64 bit complex floating-point multiplier with 64bit IEEE 754 format multipliers having less delay. Vedic multiplier of ripple carry adder based is suggested for mantissa multiplication in IEEE 754 format. Suggested Vedic multiplier uses historic Vedic Indian mathematics sutra called Urdhva-Tiryagbhyam for Vedic multiplication. The architecture Proposed for 64x64 bit complex floating-point multiplier is in Xilinx ISE 14.2 FPGA navigator in Verilog HDL. Eventually, the outcomes of the suggested multiplier will differentiate with traditional booth multiplier and array multiplier which represents clearly that complex multiplication using suggested architecture gives less delay, power and low area.

Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier

Many applications, such as machine learning and sensor data analysis, are statistical in nature and can tolerate some level of inaccuracy in their computation. Approximate computing is a viable method to save energy and increase performance by controllably trading off energy for accuracy. In this paper, we propose a tiered approximate floating point multiplier, called CFPU, which significantly reduces energy consumption and improves the performance of multiplication at a slight cost in accuracy. The floating point multiplication is approximated by replacing the costly mantissa multiplication step of the operation with lower energy alternatives. We process the data by using one of the three modes: a basic approximate mode, an intermediate approximate mode, or on the exact hardware, depending on the accuracy requirements. We evaluate the efficiency of the proposed CFPU on a wide range of applications including twelve general OpenCL ones and three machine learning applications. Our results show that using the first CFPU approximation mode results in $3.5\times $ energy-delay product (EDP) improvement, compared to a GPU using traditional floating point units (FPUs), while ensuring less than 10% average relative error. Adding the second mode further increases the EDP improvement to $4.1\times $ , compared to an unmodified FPU, for less than 10% error. In addition, our results show that the proposed CFPU can achieve $2.8\times $ EDP improvement for multiply operations as compared to state-of-the-art approximate multipliers.

Reconfigurable half-precision floating-point real/complex fused multiply and add unit

Multiplication followed by an addition/subtraction is the common operation in many digital signal and image processing applications. This paper presents a reconfigurable floating-point real/complex fused multiply and add (R/C-FMA) unit using small precision (IEEE-754-2008 16-bit half-precision) format. The developed FMA can be reconfigurable from real to complex based on the control bits. This architecture performs real FMA [(a × b) + c], complex FMA {[(a + ib) × (c + id)] + (e + if)} or mixed real and complex FMA {[(a + ib) × (c + id)] + e}. The field programmable gate array (FPGA) implementation of R/C-FMA design, utilises the modern features of inbuilt DSP blocks for mantissa multiplication and addition/subtraction. The efficient DSP usage for fp16 FMA design shows a 60% reduction in LUT area when compared to conventional fp32 FMA.

Reconfigurable half-precision floating-point real/complex fused multiply and add unit

Multiplication followed by an addition/subtraction is the common operation in many digital signal and image processing applications. This paper presents a reconfigurable floating-point real/complex fused multiply and add (R/C-FMA) unit using small precision (IEEE-754-2008 16-bit half-precision) format. The developed FMA can be reconfigurable from real to complex based on the control bits. This architecture performs real FMA [(a × b) + c], complex FMA {[(a + ib) × (c + id)] + (e + if)} or mixed real and complex FMA {[(a + ib) × (c + id)] + e}. The field programmable gate array (FPGA) implementation of R/C-FMA design, utilises the modern features of inbuilt DSP blocks for mantissa multiplication and addition/subtraction. The efficient DSP usage for fp16 FMA design shows a 60% reduction in LUT area when compared to conventional fp32 FMA.

Design of quadruple precision multiplier architectures with SIMD single and double precision support

This paper proposes architectures for dual-mode and tri-mode dynamically configurable multiplier for quadruple precision arithmetic. The proposed dual-mode QPdDP multiplier architectures can either compute on a pair of quadruple precision (QP) operands or provide SIMD support for two-parallel (dual) sets of double precision (DP) operands. The proposed tri-mode QPdDPqSP multiplier architectures are aimed to include the four-parallel (quad) single precision (SP) along with dual-DP and a QP operand processing. For the underlying largest sub-component, the mantissa multiplier, two methods are analyzed to design the dual-mode/tri-mode architectures. One is based on the Karatsuba method, and in another a dual-mode/tri-mode Radix-4 Modified Booth (MB) multiplier is proposed. The proposed dual-mode/tri-mode MB multiplier requires few extra 2:1 MUXs as an overhead compared to a simple MB multiplier. To support dual-mode/tri-mode functioning other important sub-components of the FP multiplication are also re-designed for multi-mode support. The proposed architectures are synthesized using UMC 90 nm ASIC technology, and are compared against prior literature in terms of area, period, and a unified metric “Area (Gate Count) × Period (FO4) × Latency × Throughput (in cycles)”. The dual-mode/tri-mode FP architectures with MB mantissa multipliers shows better timings, however, those with Karatsuba mantissa multipliers acquires smaller area.

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques . Further , the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques . Further , the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.

Efficient dual-precision floating-point fused-multiply-add architecture

The fused-multiply-add (FMA) instruction is a common instruction in RISC processors since 1990. A 3-stage, 8-level pipelined, dual-precision FMA is proposed here that can perform operations either at one double precision (SISD) or at two single precision in parallel (SIMD). The 53-bit mantissa-multiplier (MM) is optimally segmented by Karatsuba–Offman (KO) algorithm such that both modes can be performed. The 6-stage pipelined MM uses only 6 of 10 multipliers and 13 of 33 adder/subtractors in SIMD. Thus hardware area of the proposed MM is reduced by 23.82% and throughput is maintained to be 923M samples/s. The arithmetic operational units in the data path are shared among the modes by having four data rearrangement units (DRU) which rearranges the data systematically at the input, the outputs of MM and the final output. Though these DRUs bring some hardware overhead, the resulting architecture is modular and uniform for both modes of computation. The proposed FMA has been implemented using TSMC 1P6M CMOS 130 nm library and takes 48% less overall area and consumes 49% less power at 308.7 MHz compared to previous results. The area-delay-product (ADP), 0.48 × 10−15 shows that the area optimization by proposed KO based MM can also keep the computation time as 3.24 ns.