Majority-logic Decoding Research Articles

Convolutional Codec Implemented by Genetic Circuits for Molecular Communication.

Molecular communication (MC), which transmits information through molecules, has emerged as a promising technique to enable communication links between nanomachines. To establish information transmission using molecules, synthetic biology through genetic circuits techniques can be utilized to construct biological components. Recent efforts on genetic circuits have produced many exciting MC systems and generated substantial insights. With basic gene regulatory modules and motifs, researchers are now constructing artificial networks with novel functions that will serve as building blocks in the MC system. In this paper, we investigate the design of genetic circuits to implement the convolutional codec in a diffusion-based MC channel with the concentration shift keying (CSK) transmission scheme. At the receiver, a majority-logic decoder is applied to decode the received symbols. These functions are completely realized in the field of biochemistry through the activation and inhibition of genes and biochemical reactions, rather than through classical electrical circuits. Biochemical simulations are used to verify the feasibility of the system and analyze the impairments caused by diffusion noise and chemical reaction noise of genetic circuits.

Low Complexity Majority-Logic Decoding for LDPC-Coded PNC Systems

In this letter, we propose majority-logic decoding (MLGD) algorithms of low complexity for low-density parity-check (LDPC) coded physical-layer network coding (PNC) in a two-way relay channel (TWRC). In particular, we decode the transmit combination of two-user messages from the superimposed signal and then map the XOR message of two users. By exploiting the superposition rules of PNC, we develop hard decision-based and reliability-based decoding algorithms, i.e., modified one-step MLGD (M-OSMLGD) and iterative soft reliability-based decoding (M-ISRB), to iteratively update the combination of two-user messages. Moreover, we propose an improved M-ISRB (IM-ISRB) decoding to update the external reliability of the combination of two-user messages in each iteration. Simulation results show that the proposed decoding algorithms can achieve effective an trade-off between complexity and decoding performance for LDPC-coded PNC systems.

Majority Logic Decoding for Certain Schubert Codes Using Lines in Schubert Varieties

In this article, we consider Schubert codes, linear codes associated to Schubert varieties, and discuss minimum weight codewords for dual Schubert codes. The notion of lines in Schubert varieties is looked closely at, and it has been proved that the supports of the minimum weight codewords of the dual Schubert codes lie on lines and any three points on a line in Schubert variety correspond to the support of some minimum weight parity check for the Schubert code. We use these lines in Schubert varieties to construct orthogonal parity checks for certain Schubert codes and use them for majority logic decoding. In some special cases, we can correct approximately up to $\lfloor (d-1)/2\rfloor$ many errors where $d$ is the minimum distance of the code.

Guessing Random Additive Noise Decoding With Symbol Reliability Information (SRGRAND)

The design and implementation of error correcting codes has long been informed by two fundamental results: Shannon’s 1948 capacity theorem, which established that long codes use noisy channels most efficiently; and Berlekamp, McEliece, and Van Tilborg’s 1978 theorem on the NP-completeness of decoding linear codes. These results shifted focus away from creating code-independent decoders, but recent low-latency communication applications necessitate relatively short codes, providing motivation to reconsider the development of universal decoders. We introduce a scheme for employing binarized symbol soft information within Guessing Random Additive Noise Decoding, a universal hard detection decoder. We incorporate codebook-independent quantization of soft information to indicate demodulated symbols to be reliable or unreliable. We introduce two decoding algorithms: one identifies a conditional Maximum Likelihood (ML) decoding; the other either reports a conditional ML decoding or an error. For random codebooks, we present error exponents and asymptotic complexity, and show benefits over hard detection. As empirical illustrations, we compare performance with majority logic decoding of Reed-Muller codes, with Berlekamp-Massey decoding of Bose-Chaudhuri-Hocquenghem codes, with CA-SCL decoding of CA-Polar codes, and establish the performance of Random Linear Codes, which require a universal decoder and offer a broader palette of code sizes and rates than traditional codes.

Point-line incidence on Grassmannians and majority logic decoding of Grassmann codes

In this article, we consider the decoding problem of Grassmann codes using majority logic. We show that for two points of the Grassmannian, there exists a canonical geodesic between these points once a complete flag is fixed. These geodesics are used to construct a large set of parity checks orthogonal on a coordinate of the code, resulting in a majority decoding algorithm.

Erasing a majority-logic bit

We study finite-time bit erasure in the context of majority-logic decoding. In particular, we calculate the minimum amount of work needed to erase a majority-logic bit when one has full control over the system dynamics. We show that although a single unit bit is easier to erase in the slow-driving limit, the majority-logic bit in general outperforms the single unit bit in the fast-erasure limit. Our results also suggest optimal design principles for majority-logic bits under limited control.

An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes

When non-binary low-density parity-check (NB-LDPC) codes with low column weights are adopted, the iterative reliability-based majority-logic decoding (IRB-MLGD) algorithms suffer from severe performance degradation compared to message passing algorithms. In this brief, based on the improved iterative soft reliability-based (IISRB)-MLGD algorithm, we propose a perturbation-injected (P)-IISRB algorithm, where a regular perturbation is introduced to alleviate the periodic point problem that is the main reason for IISRB decoding failure. Compared with the conventional IISRB, the new algorithm significantly improves the decoding performance, lowering the error-floor by at least two orders of magnitude for the example code. Besides, instead of traditionally pre-computing and storing all the q-ary channel reliability measures, a real-time computing method is presented, which reduces the memory cost from <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( q) to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> q).

Majority Logic Decoding With Subspace Designs

Rudolph (1967) introduced one-step majority logic decoding for linear codes derived from combinatorial designs. The decoder is easily realizable in hardware and requires that the dual code has to contain the blocks of so called geometric designs as codewords. Peterson and Weldon (1972) extended Rudolph's algorithm to a two-step majority logic decoder correcting the same number of errors as Reed's celebrated multi-step majority logic decoder. Here, we study the codes from subspace designs. It turns out that these codes have the same majority logic decoding capability as the codes from geometric designs, but their majority logic decoding complexity is sometimes drastically improved. For a known infinite series of subspace designs the reduction of complexity is exponential.

Nonbinary Low-Density Parity Check Decoding Algorithm Research-Based Majority Logic Decoding

In the nonbinary low-density parity check (NB-LDPC) codes decoding algorithms, the iterative hard reliability based on majority logic decoding (IHRB-MLGD) algorithm has poor error correction performance. The essential reason is that the hard information is used in the initialization and iterative processes. For the problem of partial loss of information, when the reliability is assigned during initialization, the error correction performance is improved by modifying the assignment of reliability at initialization. The initialization process is determined by the probability of occurrence of the number of erroneous bits in the symbol and the Hamming distance. In addition, the IHRB-MLGD decoding algorithm uses the hard decision in the iterative decoding process. The improved algorithm adds soft decision information in the iterative process, which improves the error correction performance while only slightly increasing the decoding complexity, and improves the reliability accumulation process which makes the algorithm more stable. The simulation results indicate that the proposed algorithm has a better decoding performance than IHRB algorithm.

Efficient Design to Error Detection in EG-LDPC Codes

Capability to correct large number of errors Majority logic decodable codes is suitable for memory applications. The memory access time as well as area of utilization and the decoding time is reducing using Majority Logic Decoder. In Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes there exits fault secure detector which are used for error correction. Because EG-LDPC codes are widely used it will avoid high complexity in decoding. Majority logic decidable which is a one step is a technique similar to a class of Euclidean geometry low density parity check (EG-LDPC) codes. This method is very effective for EG-LDPC codes as shown in the result. The number of errors are detected by the majority logic decode further it can be used for correct the errors which occurred.

Gradient-descent decoding of one-step majority-logic decodable codes

In this paper, a new low-complexity gradient-descent based iterative majority-logic decoder (GD-MLGD) is proposed for decoding One-Step Majority-Logic Decodable (OSMLD) codes. We give a formulation of the decoding problem of binary OSMLD codes, as a maximization problem of a derivable objective function. The optimization problem is solved using a pseudo gradient-descent algorithm, which performs iteratively an update towards the optimal estimated codeword been transmitted, based on the first-order partial derivatives of each variable calculated in the previous iteration. The proposed decoding scheme achieves a fast convergence to an optimum codeword compared to other decoding techniques reviewed in this paper, at the cost of lower computational complexity. The quantized version (QGD-MLGD) is also proposed in order to further reduce the computational complexity. Simulation results show that the proposed decoding algorithms outperform all the existing majority-logic decoding schemes, and also various gradient-descent based bit-flipping algorithms, and performs nearly close to the belief propagation sum–product (BP-SP) decoding algorithm of LDPC codes, especially for high code lengths, providing an efficient trade-off between performance and decoding complexity. Moreover, the proposed quantized algorithm has shown to perform better than all the existing decoding techniques. The proposed decoding algorithms have shown to be suitable for ultra reliable, low latency and energy-constrained communication systems where both high performances and low-complexity are required.

Implementation Of Logic Fault Detection Techniques Using Fpga 1232 Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP) © Copyright: All rights reserved. Retrieval Number: F12110986S319/2019©BEIESP DOI:10.35940/ijeat.F1211.0986S319 Journal Website: www.ijeat.org Fig. 1. Block diagram of Simple Memory System III. LOGIC FAULT DETECTION TECHNIQUES A. Normal Majority Logic (ML) Decoder The fault present in the input can be corrected by

The evolution of automation concept in industries and rising significance for digital mode of communication have in turn stresses the need for reliable, efficient and high performance digital system. One of the major problems faced in the digital transmission is the loss of data and hence an effective technique to detect and correct these faults is necessary. Conventionally, various techniques are used for this purpose. Among them, three of the techniques like Plain Majority Logic (ML) Decoder, Syndrome Fault Detector and Plain ML Detector Decoder (MLDD) are analyzed and compared in this paper. The purpose of this comparison is to identify the most suitable methodology based on its capability to track maximum number of faults in minimum number of cycles, with reduced memory read access time. All these logics are simulated using HDL code and analysis is done to implement it in FPGA. The results reveal that Plain MLDD is found to provide better solution for various digital circuits than other techniques.

A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes

The majority logic (ML) gate (MLG) is required in fast decoder implementations to protect memories from transient soft errors. In this paper, a novel MLG design is proposed; it consists of a pMOS pull-up network, an nMOS pull-down network, and an inverter. The proposed design is applicable to an arbitrary number of inputs $\gamma $ (and operating as a mirror circuit when $\gamma $ is odd). The proposed designs are simply requiring a small number of transistors; when simulated, they offer improved metrics such as reduction in delay, area, and power dissipation compared with existing designs found in the technical literature. When the combined power-delay-area product (PDAP) is considered, the advantages of the proposed designs are pronounced. The application of the proposed MLGs to design fast decoders for one-step ML decodable (OS-MLD) codes is also presented; the results show that the proposed MLGs are very efficient circuits for this coding application.

Error Correction Codes Derived from Orthogonal Latin Square Codes

The developments in IC technology and rapid increase of transistor densities and scaling factor, the use of ECC’s acquired prominence. Multiple bit errors in memories due to technology scaling demands advanced error correction codes. SEC-DEC, DEC, burst error detection, Golay code, Reed Solmon codes etc. have much decoding complexity and latency. The above drawbacks can be reduced with OLS codes. OLS codes with majority logic decoding technique, modular construction and simple decoding mechanisms it enables low delay improvements. MBU’S can be addressed using OLS-MLD codes. This paper presents a detail study of developments in multibit ECC’s using OLS-MLD mechanism

A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes

Non-binary low-density parity-check (NB-LDPC) codes usually exhibit much better performance than their binary counterparts. Among NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding (MLGD) algorithms are attractive for their low computation complexity, at the cost of performance degradation. In this brief, based on the improved iterative soft reliability-based (IISRB)-MLGD algorithm, we propose a clipped-modified (CM)-IISRB algorithm, which achieves better decoding performance with lower computational complexity. First, two modifications are introduced to the IISRB algorithm, which considerably reduces the decoding complexity with negligible performance loss. Second, an unsaturated-clipping method that facilitates significant performance improvement is presented. Simulation results show that the new algorithm outperforms the IISRB by about 0.2dB for the 256-ary (255, 175) example code. Moreover, based on a new storage reduction method, an optimized architecture is developed for the CM-IISRB algorithm. Synthesis results demonstrate that the proposed decoder can achieve very low hardware complexity, comparable to that of the iterative hard reliability-based (IHRB) decoder.

Distributed Reed Muller Code with Multiple Relays for Cooperative Broadband Wireless Networks

The authors have investigated the bit-error rate (BER) performance of Reed-Muller coded cooperative single-carrier frequency domain equalization (RMCC-SC-FDE) scheme and Reed-Muller coded cooperativeOFDM(RMCC-OFDM) scheme incorporating multiple relays and multiple antennas. The maximum ratio combining (MRC) technique is utilized for OFDM/SC-FDE signal detection at the destination terminal. The joint soft maximum likelihood decoding (JSMLD) and the joint majority logic decoding (JMLD) are employed at the destination terminal. The deployment of multiple relays have invigorated the BER performance of RMCC-OFDM and RMCC-SC-FDE schemes. Numerical results demonstrate that the RMCC-SC-FDE scheme exhibits a betterBERperformance over theRMCC-OFDM scheme in identical conditions. Furthermore, the simulated results reveal that the RMCC-SC-FDE and RMCC-OFDM schemes not only yield a better BER performance gain over their corresponding non-cooperative coded counterpart schemes but also outperform the turbo coded cooperative SC-FDE and turbo coded cooperative OFDM schemes, respectively, under identical conditions.

Adaptive 2-D Scheduling-Based Nonbinary Majority-Logic Decoding for NAND Flash Memory

This brief presents a nonbinary adaptive 2D scheduling-based majority logic decoding (NB-ATS-MLGD) algorithm for NAND flash memory. The proposed algorithms provide considerable tradeoff between error-correcting capability and decoding complexity, and make the NB-MLGD decoding more attractive for practical purposes in the multi-level cells (MLC) NAND flash memory. The most significant feature of the proposed NB-ATS-MLGD algorithm is the 2D layered scheduling strategy, where the decoding orders of check nodes (CNs) and variable nodes (VNs) are both adaptive. By leveraging on the MLC flash memory bit error patterns, an early-correcting (EC) criterion is incorporated into the NB-ATS-MLGD algorithm. Furthermore, the simplification and parallelization of proposed algorithms make them more practical in NAND flash memory. Simulation results show that the proposed algorithms increase the lifetime of MLC flash memory up to 3000 program-and-erase (PE) cycles and have desirable convergence speed compared with the conventional non-binary MLGD algorithm. When at low PE cycles, the NB-EC-ATS-MLGD algorithm improves frame error rate (FER) performance by more than 3 order of magnitudes compared with the conventional non-binary MLGD algorithm.

Multiple relay‐based Reed–Muller network‐coded cooperation for wireless communication system

This research article proposes a multiple relay-based Reed–Muller network-coded cooperative (MR-RMNCC) scheme for wireless communication. In the MR-RMNCC scheme, Hadamard transform construction is adopted to build Reed–Muller (RM) codes that effectively achieve network coded-cooperation among multiple sources and multiple relays over slow and fast Rayleigh fading channels. In any network coded-cooperative system, a proper encoding strategy at the relay nodes is vital for achieving an optimum code construction at the destination node. Therefore, the authors have proposed an efficient message bit selection algorithm at relay-2 that optimally selects the message bits. The supremacy of the message bit selection algorithm is demonstrated by Monte–Carlo simulation. Furthermore, the performance bound for average error-probability is also derived for the MR-RMNCC scheme that validates its simulated bit-error-rate performance over a fast Rayleigh fading channel. At the destination node, the MR-RMNCC scheme is jointly decoded by two different decoding strategies, i.e. joint soft maximum likelihood decoding and joint majority logic decoding. Monte–Carlo simulations suggest that the MR-RMNCC scheme not only provides a significant bit-error-rate performance gain over its corresponding coded non-cooperative scheme but also to the existing state-of-the-art RM network-coded cooperative scheme under identical conditions.

An Efficient Majority Error Detection in Logic Decoding with Euclidean Geometry Low Density Parity Check (Eg-Ldpc) Codes

In a recent article, a technique was proposed to step up the majority logic decoding of variation set low density parity check codes. This is helpful as majority logic decoding can be implemented serially with trouble-free hardware but requires a huge decoding time. The method detect whether a word has errors in the initial iterations of majority logic decoding, and at what time there are no errors the decoding split ends without completing the rest of the iterations. While the majority words in a memory will be error-free, the average decoding time is significantly reduced. The outcome obtained proves that the technique is also effective for EG-LDPC codes. General simulation results are given to precisely estimate the prospect of error detection for different code sizes and numbers of errors.

Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes

Error Correction Codes (ECCs) are commonly used to protect memories against soft errors with an impact on memory area and delay. For large memories, the area overhead is mostly due to the additional cells needed to store the parity check bits. In terms of delay, the overhead is mostly needed to detect and correct errors when the data is read from the memory. Most ECCs that can correct more than one error have a complex decoding process and so are limited in high speed memory applications. One exception is One Step Majority Logic Decodable (OS-MLD) codes for which decoding can be done in parallel at high speed. Unfortunately, there are only a few OS-MLD codes that provide a limited choice in terms of block sizes, error correction capabilities and code rate. Therefore, there is considerable interest in a novel construction of OS-MLD codes to provide additional choices for protecting memories. In this paper, a new method to construct Double Error Correction (DEC) OS-MLD codes is presented. This method is based on the use of parity check matrices in which two bits have at most two parity check equations in common; the proposed method provides codes that require a smaller number of parity check bits than existing codes like Orthogonal Latin Square (OLS) codes. The drawback of the proposed Two Bit Overlap (TBO) codes is that they require slightly more complex decoding than OLS codes. Therefore, they provide an intermediate solution between OLS and non OS-MLD codes in terms of decoding delay and number of parity check bits. The proposed TBO codes have been implemented for some block sizes and compared to both OLS and BCH codes to illustrate the trade off in delay and memory overhead. Finally, this paper discusses the generalization of the proposed scheme to codes with larger error correction capabilities.