Majority Logic Decodable Codes Research Articles

Efficient Design to Error Detection in EG-LDPC Codes

Capability to correct large number of errors Majority logic decodable codes is suitable for memory applications. The memory access time as well as area of utilization and the decoding time is reducing using Majority Logic Decoder. In Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes there exits fault secure detector which are used for error correction. Because EG-LDPC codes are widely used it will avoid high complexity in decoding. Majority logic decidable which is a one step is a technique similar to a class of Euclidean geometry low density parity check (EG-LDPC) codes. This method is very effective for EG-LDPC codes as shown in the result. The number of errors are detected by the majority logic decode further it can be used for correct the errors which occurred.

Gradient-descent decoding of one-step majority-logic decodable codes

In this paper, a new low-complexity gradient-descent based iterative majority-logic decoder (GD-MLGD) is proposed for decoding One-Step Majority-Logic Decodable (OSMLD) codes. We give a formulation of the decoding problem of binary OSMLD codes, as a maximization problem of a derivable objective function. The optimization problem is solved using a pseudo gradient-descent algorithm, which performs iteratively an update towards the optimal estimated codeword been transmitted, based on the first-order partial derivatives of each variable calculated in the previous iteration. The proposed decoding scheme achieves a fast convergence to an optimum codeword compared to other decoding techniques reviewed in this paper, at the cost of lower computational complexity. The quantized version (QGD-MLGD) is also proposed in order to further reduce the computational complexity. Simulation results show that the proposed decoding algorithms outperform all the existing majority-logic decoding schemes, and also various gradient-descent based bit-flipping algorithms, and performs nearly close to the belief propagation sum–product (BP-SP) decoding algorithm of LDPC codes, especially for high code lengths, providing an efficient trade-off between performance and decoding complexity. Moreover, the proposed quantized algorithm has shown to perform better than all the existing decoding techniques. The proposed decoding algorithms have shown to be suitable for ultra reliable, low latency and energy-constrained communication systems where both high performances and low-complexity are required.

A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes

The majority logic (ML) gate (MLG) is required in fast decoder implementations to protect memories from transient soft errors. In this paper, a novel MLG design is proposed; it consists of a pMOS pull-up network, an nMOS pull-down network, and an inverter. The proposed design is applicable to an arbitrary number of inputs $\gamma $ (and operating as a mirror circuit when $\gamma $ is odd). The proposed designs are simply requiring a small number of transistors; when simulated, they offer improved metrics such as reduction in delay, area, and power dissipation compared with existing designs found in the technical literature. When the combined power-delay-area product (PDAP) is considered, the advantages of the proposed designs are pronounced. The application of the proposed MLGs to design fast decoders for one-step ML decodable (OS-MLD) codes is also presented; the results show that the proposed MLGs are very efficient circuits for this coding application.

Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes

Error Correction Codes (ECCs) are commonly used to protect memories against soft errors with an impact on memory area and delay. For large memories, the area overhead is mostly due to the additional cells needed to store the parity check bits. In terms of delay, the overhead is mostly needed to detect and correct errors when the data is read from the memory. Most ECCs that can correct more than one error have a complex decoding process and so are limited in high speed memory applications. One exception is One Step Majority Logic Decodable (OS-MLD) codes for which decoding can be done in parallel at high speed. Unfortunately, there are only a few OS-MLD codes that provide a limited choice in terms of block sizes, error correction capabilities and code rate. Therefore, there is considerable interest in a novel construction of OS-MLD codes to provide additional choices for protecting memories. In this paper, a new method to construct Double Error Correction (DEC) OS-MLD codes is presented. This method is based on the use of parity check matrices in which two bits have at most two parity check equations in common; the proposed method provides codes that require a smaller number of parity check bits than existing codes like Orthogonal Latin Square (OLS) codes. The drawback of the proposed Two Bit Overlap (TBO) codes is that they require slightly more complex decoding than OLS codes. Therefore, they provide an intermediate solution between OLS and non OS-MLD codes in terms of decoding delay and number of parity check bits. The proposed TBO codes have been implemented for some block sizes and compared to both OLS and BCH codes to illustrate the trade off in delay and memory overhead. Finally, this paper discusses the generalization of the proposed scheme to codes with larger error correction capabilities.

Soft Error Tolerance in Memory Applications

This paper proposes a new method to detect and correct multi bit errors in memory applications using a combination of a clustering approach, Bit-Per-Byte error detection technique, and Majority Logic Decodable (MLD) codes. The likelihood of soft errors accelerates with system complexity, reduction in operational voltages, exponential growth in transistor per chip, increases in clock frequencies, breakdown of memory reliability and device shrinking. Memories are the sensitive part of a computer system. Soft errors in memories may cause an instruction to malfunction. Several techniques are already in practice to mitigate the soft errors. Majority logic decodable codes are proved as effective for memory applications because of their ability to correct a massive number of errors. Since memories are used to hold large number of bits that’s the restraint of Majority logic decodable codes method, so we emphasize on the size of data word in this method. The proposed method aims to detect and correct up to seven bit errors with lesser computational time. It works in an efficient manner in case of adjacent errors which is not possible in Majority logic decodable codes (MLD). It is delineated by Experimental reviews that the proposed approach outperforms existing dominant approach with respect to number of erroneous bit detection and correction, and computational time overhead.

Binary Linear Locally Repairable Codes

Locally repairable codes (LRCs) are a class of codes designed for the local correction of erasures. They have received considerable attention in recent years due to their applications in distributed storage. Most existing results on LRCs do not explicitly take into consideration the field size $q$ , i.e., the size of the code alphabet. In particular, for the binary case, only a few results are known. In this paper, we present an upper bound on the minimum distance $d$ of linear LRCs with availability, based on the work of Cadambe and Mazumdar. The bound takes into account the code length $n$ , dimension $k$ , locality $r$ , availability $t$ , and field size $q$ . Then, we study the binary linear LRCs in three aspects. First, we focus on analyzing the locality of some classical codes, i.e., cyclic codes and Reed–Muller codes, and their modified versions, which are obtained by applying the operations of extend, shorten, expurgate, augment, and lengthen. Next, we construct LRCs using phantom parity-check symbols and multi-level tensor product structure, respectively. Compared with other previous constructions of binary LRCs with fixed locality or minimum distance, our construction is much more flexible in terms of code parameters, and gives various families of high-rate LRCs, some of which are shown to be optimal with respect to their minimum distance. Finally, the availability of LRCs is studied. We investigate the locality and availability properties of several classes of one-step majority-logic decodable codes, including cyclic simplex codes, cyclic difference-set codes, and 4-cycle free regular low-density parity-check codes. We also show the construction of a long LRC with availability from a short one-step majority-logic decodable code.

Convergence Analysis of Iterative Threshold Decoding Process

Today the error correcting codes are present in all the telecom standards, in particular the low density parity check (LDPC) codes. The choice of a good code for a given network is essentially linked to the decoding performance obtained by the bit error rate (BER) curves. This approach requires a significant simulation time proportional to the length of the code, to overcome this problem Exit chart was introduced, as a fast technique to predict the performance of a particular class of codes called Turbo codes. In this paper, we success to apply Exit chart to analyze convergence behavior of iterative threshold decoding of one step majority logic decodable (OSMLD) codes. The iterative decoding process uses a soft-input soft-output threshold decoding algorithm as component decoder. Simulation results for iterative decoding of simple and concatenated codes transmitted over a Gaussian channel have shown that the thresholds obtained are a good indicator of the Bit Error Rate (BER) curves.

Reliability-based iterative proportionality-logic decoding of LDPC codes with adaptive decision

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

A Method to Extend Orthogonal Latin Square Codes

Error correction codes (ECCs) are commonly used to protect memories from errors. As multibit errors become more frequent, single error correction codes are not enough and more advanced ECCs are needed. The use of advanced ECCs in memories is, however, limited by their decoding complexity. In this context, one-step majority logic decodable (OS-MLD) codes are an interesting option as the decoding is simple and can be implemented with low delay. Orthogonal Latin squares (OLS) codes are OS-MLD and have been recently considered to protect caches and memories. The main advantage of OLS codes is that they provide a wide range of choices for the block size and the error correction capabilities. In this brief, a method to extend OLS codes is presented. The proposed method enables the extension of the data block size that can be protected with a given number of parity bits thus reducing the overhead. The extended codes are also OS-MLD and have a similar decoding complexity to that of the original OLS codes. The proposed codes have been implemented to evaluate the circuit area and delay needed for different block sizes.

Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes

This paper presents two iterative decoding algorithms for a class of non-binary two-step majority-logic (NB-TS-MLG) decodable cyclic codes. A partial parallel decoding scheme is also introduced to provide a balanced trade-off between decoding speed and storage requirements. Unlike non-binary one-step MLG decodable cyclic codes, the Tanner graphs of which are 4-cycle-free, NB-TS-MLG decodable cyclic codes contain a large number of short cycles of length 4, which tend to degrade decoding performance. The proposed algorithms utilize the orthogonal structure of the parity-check matrices of the codes to resolve the degrading effects of the short cycles of length 4. Simulation results demonstrate that the NB-TS-MLG decodable cyclic codes decoded with the proposed algorithms offer coding gains as much as 2.5 dB over Reed-Solomon codes of the same lengths and rates decoded with either hard-decision or algebraic soft decision decoding.

Joint detection/decoding algorithms for non‐binary low‐density parity‐check codes over inter‐symbol interference channels

This study is concerned with the application of non-binary low-density parity-check (NB-LDPC) codes to binary input inter-symbol interference channels. Two low-complexity joint detection/decoding algorithms are proposed. One is referred to as max-log-MAP/X-EMS algorithm, which is implemented by exchanging soft messages between the max-log-MAP detector and the extended min-sum (EMS) decoder. The max-log-MAP/X-EMS algorithm is applicable to general NB-LDPC codes. The other one, referred to as Viterbi/GMLGD algorithm, is designed in particular for majority-logic decodable NB-LDPC codes. The Viterbi/GMLGD algorithm works in an iterative manner by exchanging hard-decisions between the Viterbi detector and the generalised majority-logic decoder (GMLGD). As a by-product, a variant of the original EMS algorithm is proposed, which is referred to as µ-EMS algorithm. In the µ-EMS algorithm, the messages are truncated according to an adaptive threshold, resulting in a more efficient algorithm. Simulations results show that the max-log-MAP/X-EMS algorithm performs as well as the traditional iterative detection/decoding algorithm based on the BCJR algorithm and theQ-ary sum–product algorithm, but with lower complexity. The complexity can be further reduced for majority-logic decodable NB-LDPC codes by executing the Viterbi/GMLGD algorithm with a performance degradation within one dB. These algorithms provide good candidates for trade-offs between performance and complexity.

A new class of majority-logic decodable codes derived from polarity designs

The polarity designs, introduced in [9], are combinatorial 2-designs having the same parameters as a projective geometry design $PG_s(2s,q)$ formed by the $s$-subspaces of $PG(2s,q)$, $s\ge 2$, $q=p^t$, $p$ prime. If $q=p$ is a prime, a polarity design has also the same $p$-rank as $PG_s(2s,p)$. If $q=2$, any polarity 2-design is extendable to a 3-design having the same parameters and 2-rank as an affine geometry design $AG_{s+1}(2s+1,2)$ formed by the $(s+1)$-subspaces of $AG(2s+1,2)$. It is shown in this paper that a linear code being the null space of the incidence matrix of a polarity design can correct by majority-logic decoding the same number of errors as the projective geometry code based on $PG_s(2s,q)$. In the binary case, any polarity 3-design yields a binary self-dual code with the same parameters, minimum distance, and correcting the same number of errors by majority-logic decoding as the Reed-Muller code of length $2^{2s+1}$ and order $s$.

Multiple Cell Upset Correction in Memories Using Difference Set Codes

Error Correction Codes (ECCs) are commonly used to protect memories from soft errors. As technology scales, Multiple Cell Upsets (MCUs) become more common and affect a larger number of cells. An option to protect memories against MCUs is to use advanced ECCs that can correct more than one error per word. In this area, the use of one step majority logic decodable codes has recently been proposed for memory applications. Difference Set (DS) codes are one example of these codes. In this paper, a scheme is presented to protect a memory from MCUs using Difference Set codes. The proposed scheme exploits the localization of the errors in an MCU, as well as the properties of DS codes, to provide enhanced error correction capabilities. The properties of the DS codes are also used to reduce the decoding time. The scheme has been implemented in HDL, and circuit area and speed estimates are provided.

A (64,45) Triple Error Correction Code for Memory Applications

Memories are commonly protected with error correction codes to avoid data corruption when a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This is because they are simple to implement and provide low latency. More advanced codes have been considered, but their main drawback is the complexity of the decoders and the added latency. Recently, the use of one-step majority logic decodable codes has been proposed for memory protection. One-step majority logic decoding enables the use of low-complexity decoders, and low latency can also be achieved with moderate complexity. The main issue is that there are only a few codes that are one-step majority logic decodable. This restricts the choice of word lengths and error correction capabilities. In this paper, a method to derive new codes from a class of one-step majority logic decodable codes known as difference-set codes is proposed. The derived codes can also be efficiently implemented. As an example, a (64,45) triple error correction (TEC) code is derived and compared with existing SEC and TEC codes. The results presented enable a wider choice of word lengths and error correction capabilities that will be useful for memory designs.

Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications

Nowadays, single event upsets (SEUs) altering digital circuits are becoming a bigger concern for memory applications. This paper presents an error-detection method for difference-set cyclic codes with majority logic decoding. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low.

Iterative Algorithms for Decoding a Class of Two-Step Majority-Logic Decodable Cyclic Codes

Codes constructed based on finite geometries form a large class of cyclic codes with large minimum distances which can be decoded with simple majority-logic decoding in one or multiple steps. In 2001, Kou, Lin and Fossorier showed that the one-step majority-logic decodable finite geometry codes form a class of cyclic LDPC codes whose Tanner graphs are free of cycles of length 4. These cyclic finite geometry LDPC codes perform very well over the AWGN channel using iterative decoding based on belief propagation (IDBP) and have very low error-floors. However, the standard IDBP is not effective for decoding other cyclic finite geometry codes because their Tanner graphs contain too many short cycles of length 4 which severely degrade the decoding performance. This paper investigates iterative decoding of two-step majority-logic decodable finite geometry codes. Three effective algorithms for decoding these codes are proposed. These algorithms are devised based on the orthogonal structure of the parity-check matrices of the codes to avoid or reduce the degrading effect of the short cycles of length 4. These decoding algorithms provide significant coding gains over the standard IDBP using either the sum-product or the min-sum algorithms.

A New Iterative Threshold Decoding Algorithm for One Step Majority Logic Decodable Block Codes

The performance of iterative decoding algorithm for one-step majority logic decodable (OSMLD) codes is investigated. We introduce a new soft-in soft-out of APP threshold algorithm which is able to decode theses codes nearly as well as belief propagation (BP) algorithm. However the computation time of the proposed algorithm is very low. The developed algorithm can also be applied to product codes and parallel concatenated codes based on block codes. Numerical results on both AWGN and Rayleigh channels are provided. The performance of iterative decoding of parallel concatenated code (17633,8595) with rate 0.5 is only 1.8 dB away from the Shannon capacity limit at a BER of 10. General Terms Information theory and Coding, Signal Processing.

Iterative Decoding of Multiple-Step Majority Logic Decodable Codes

We investigate the performance of iterative decoding algorithms for multistep majority logic decodable (MSMLD) codes of intermediate length. We introduce a new bit-flipping algorithm that is able to decode these codes nearly as well as a maximum-likelihood decoder on the binary-symmetric channel. We show that MSMLD codes decoded using bit-flipping algorithms can outperform comparable Bose-Chaudhuri-Hocquenghem (BCH) codes decoded using standard algebraic decoding algorithms, at least for high bit-flip rates (or low and moderate signal-to-noise ratios (SNRs)).

Codes on finite geometries

New algebraic methods for constructing codes based on hyperplanes of two different dimensions in finite geometries are presented. The new construction methods result in a class of multistep majority-logic decodable codes and three classes of low-density parity-check (LDPC) codes. Decoding methods for the class of majority-logic decodable codes, and a class of codes that perform well with iterative decoding in spite of having many cycles of length 4 in their Tanner graphs, are presented. Most of the codes constructed can be either put in cyclic or quasi-cyclic form and hence their encoding can be implemented with linear shift registers.

Iterative decoding of one-step majority logic deductible codes based on belief propagation

Previously, the belief propagation (BP) algorithm has received a lot of attention in the coding community, mostly due to its near-optimum decoding for low-density parity check (LDPC) codes and its connection to turbo decoding. In this paper, we investigate the performance achieved by the BP algorithm for decoding one-step majority logic decodable (OSMLD) codes. The BP algorithm is expressed in terms of likelihood ratios rather than probabilities, as conventionally presented. The proposed algorithm fits better the decoding of OSMLD codes with respect to its numerical stability due to the fact that the weights of their check sums are often much higher than that of the corresponding LDPC codes. Although it has been believed that OSMLD codes are far inferior to LDPC codes, we show that for medium code lengths (say between 200-1000 bits), the BP decoding of OSMLD codes can significantly outperform BP decoding of their equivalent LDPC codes. The reasons for this behavior are elaborated.