A (64,45) Triple Error Correction Code for Memory Applications

Abstract

Memories are commonly protected with error correction codes to avoid data corruption when a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This is because they are simple to implement and provide low latency. More advanced codes have been considered, but their main drawback is the complexity of the decoders and the added latency. Recently, the use of one-step majority logic decodable codes has been proposed for memory protection. One-step majority logic decoding enables the use of low-complexity decoders, and low latency can also be achieved with moderate complexity. The main issue is that there are only a few codes that are one-step majority logic decodable. This restricts the choice of word lengths and error correction capabilities. In this paper, a method to derive new codes from a class of one-step majority logic decodable codes known as difference-set codes is proposed. The derived codes can also be efficiently implemented. As an example, a (64,45) triple error correction (TEC) code is derived and compared with existing SEC and TEC codes. The results presented enable a wider choice of word lengths and error correction capabilities that will be useful for memory designs.