Mainstream CPUs Research Articles

Optimising digital signal processor‐based defect detection in smart manufacturing with lightweight convolutional neural networks

AbstractIndustrial defect detection is an important part of intelligent manufacturing, and Internet of things (IoT)‐based defect detection is receiving more and more attention. Although deep learning (DL) can help defect detection reduce the cost and improve the accuracy of traditional manual quality inspection, DL requires huge computational resources and is difficult to be simply deployed on IoT devices with limited computational power and memory resources. Digital signal processor (DSP) is an important IoT device with small size, high performance and low energy consumption, which has been widely used in intelligent manufacturing. In order to perform accurate defect detection on DSP, the authors proposed various optimisation strategies and then used a parallel scheme to scale the model to execute on multiple cores. The authors’ method evaluated it on Northeastern University Surface Defect Dataset, Magnetic Tile Defect Dataset, Rail Surface Defect Dataset and Silk Cylinder Defect Dataset, and the experimental results showed that the authors’ method obtains faster speeds without accuracy loss compared to running the same Convolutional Neural Networks model on a mainstream desktop CPU. This means that the authors’ method can realise efficient and accurate defect detection on IoT devices with limited computational power and memory resources, which opens up new possibilities for future development in the field of smart manufacturing.

DSP-Based Traffic Target Detection for Intelligent Transportation

Internet of Things (IoT)-based intelligent transportation is attracting more and more attention. As a key component of intelligent transportation, traffic video monitoring is very important, in which vehicle and pedestrian detection on the road is a crucial task. Although vehicle and pedestrian detection through deep learning (DL) may achieve high accuracy, it tends to require high computing resources, which hinders its use on IoT devices. As an important class of IoT devices, digital signal processor (DSP) has the characteristics of low energy consumption, small size, and strong performance, which has been widely used in intelligent transportation. In order to use DL on DSP for accurate vehicle and pedestrian detection, we first propose a series of general tactics to optimize the object detection convolutional neural network (CNN) model, including convolution layer optimization, cache optimization, compiler optimization, intrinsics optimization and direct memory access (DMA) acceleration, and then a parallel scheme to extend the model to run on multicore, and further quantize the implementation of the model. We evaluate it on UA-DETRAC and KITTI datasets. Experimental results show that our method achieves a faster speed than running the same CNN model on a mainstream desktop CPU, with only 0.06% accuracy loss.

An O(log2N) Fully-Balanced Resampling Algorithm for Particle Filters on Distributed Memory Architectures

Resampling is a well-known statistical algorithm that is commonly applied in the context of Particle Filters (PFs) in order to perform state estimation for non-linear non-Gaussian dynamic models. As the models become more complex and accurate, the run-time of PF applications becomes increasingly slow. Parallel computing can help to address this. However, resampling (and, hence, PFs as well) necessarily involves a bottleneck, the redistribution step, which is notoriously challenging to parallelize if using textbook parallel computing techniques. A state-of-the-art redistribution takes O((log2N)2) computations on Distributed Memory (DM) architectures, which most supercomputers adopt, whereas redistribution can be performed in O(log2N) on Shared Memory (SM) architectures, such as GPU or mainstream CPUs. In this paper, we propose a novel parallel redistribution for DM that achieves an O(log2N) time complexity. We also present empirical results that indicate that our novel approach outperforms the O((log2N)2) approach.

VIP: A SIMD vectorized analytical query engine

Query execution engines for analytics are continuously adapting to the underlying hardware in order to maximize performance. Wider SIMD registers and more complex SIMD instruction sets are emerging in mainstream CPUs and new processor designs such as the many-core Intel Xeon Phi CPUs that rely on SIMD vectorization to achieve high performance per core while packing a greater number of smaller cores per chip. In the database literature, using SIMD to optimize stand-alone operators with key–rid pairs is common, yet the state-of-the-art query engines rely on compilation of tightly coupled operators where hand-optimized individual operators become impractical. In this article, we extend a state-of-the-art analytical query engine design by combining code generation and operator pipelining with SIMD vectorization and show that the SIMD speedup is diminished when execution is dominated by random memory accesses. To better utilize the hardware features, we introduce VIP, an analytical query engine designed and built bottom up from pre-compiled column-oriented data parallel sub-operators and implemented entirely in SIMD. In our evaluation using synthetic and TPC-H queries on a many-core CPU, we show that VIP outperforms hand-optimized query-specific code without incurring the runtime compilation overhead, and highlight the efficiency of VIP at utilizing the hardware features of many-core CPUs.

A performance analysis of the first generation of HPC‐optimized Arm processors

SummaryIn this paper, we present performance results from Isambard, the first production supercomputer to be based on Arm CPUs that have been optimized specifically for HPC. Isambard is the first Cray XC50 “Scout” system, combining Cavium ThunderX2 Arm‐based CPUs with Cray's Aries interconnect. The full Isambard system will be delivered in the summer of 2018, when it will contain over 10 000 Arm cores. In this work, we present node‐level performance results from eight early‐access nodes that were upgraded to B0 beta silicon in March 2018. We present node‐level benchmark results comparing ThunderX2 with mainstream CPUs, including Intel Skylake and Broadwell, as well as Xeon Phi. We focus on a range of applications and mini‐apps important to the UK national HPC service, ARCHER, as well as to the Isambard project partners and the wider HPC community. We also compare performance across three major software toolchains available for Arm: Cray's CCE, Arm's version of Clang/Flang/LLVM, and GNU.

Компиляция модели памяти OCaml в Power

The development of memory models aimed at solving various concurrency problems is an active research topic. One such model is the OCaml memory model (OCamlMM), which allows to mitigate undefined behavior caused by data races. To use this model in practice one has to prove the correctness of its compilation into mainstream CPU architectures. At the moment, it is done for x86 and ARM but not for Power.One way to prove the correctness of compilation of OCamlMM into the Power model is to develop a compilation scheme from OCamlMM into the Intermediate Memory Model (IMM). It would be sufficient since there already exists a compilation scheme from IMM to the Power model. In this paper, the compilation scheme from OCamlMM into IMM is presented and proved to be correct. Memory fences and compare-and-swap instructions are used to permit only behavior allowed by OCamlMM. The resulting compilation scheme gives a correct compilation scheme from OCamlMM to the Power model. Moreover, when a compilation scheme from IMM into another CPU architecture will be developed, such an approach would immediately give a correct scheme of compilation of OCamlMM into that architecture.

Performance of GeantV EM Physics Models

The recent progress in parallel hardware architectures with deeper vector pipelines or many-cores technologies brings opportunities for HEP experiments to take advantage of SIMD and SIMT computing models. Launched in 2013, the GeantV project studies performance gains in propagating multiple particles in parallel, improving instruction throughput and data locality in HEP event simulation on modern parallel hardware architecture. Due to the complexity of geometry description and physics algorithms of a typical HEP application, performance analysis is indispensable in identifying factors limiting parallel execution. In this report, we will present design considerations and preliminary computing performance of GeantV physics models on coprocessors (Intel Xeon Phi and NVidia GPUs) as well as on mainstream CPUs.

Scaling HTM-Supported Database Transactions to Many Cores

So far, transactional memory—although a promising technique—suffered from the absence of an efficient hardware implementation. Intel’s Haswell microarchitecture introduced hardware transactional memory (HTM) in mainstream CPUs. HTM allows for efficient concurrent, atomic operations, which is also highly desirable in the context of databases. On the other hand, HTM has several limitations that, in general, prevent a one-to-one mapping of database transactions to HTM transactions. In this work, we devise several building blocks that can be used to exploit HTM in main-memory databases. We show that HTM allows for achieving nearly lock-free processing of database transactions by carefully controlling the data layout and the access patterns. The HTM component is used for detecting the (infrequent) conflicts, which allows for an optimistic, and thus very low-overhead execution of concurrent transactions. We evaluate our approach on a four-core desktop and a 28-core server system and find that HTM indeed provides a scalable, powerful, and easy to use synchronization primitive.

A GPU-based Evolution Strategy for Optic Disk Detection in Retinal Images

Parallel processing using graphic processing units (GPUs) has attracted much research interest in recent years. Parallel computation can be applied to evolution strategy (ES) for processing individuals in a population, but evolutionary strategies are time consuming to solve large computational problems or complex fitness functions. In this paper we describe the implementation of an improved ES for optic disk detection in retinal images using the Compute Unified Device Architecture (CUDA) environment. In the experimental results we show that the computational time for optic disk detection task has a speedup factor of 5x and 7x compared to an implementation on a mainstream CPU.

BowMapCL: Burrows-Wheeler Mapping on Multiple Heterogeneous Accelerators.

The computational demand of exact-search procedures has pressed the exploitation of parallel processing accelerators to reduce the execution time of many applications. However, this often imposes strict restrictions in terms of the problem size and implementation efforts, mainly due to their possibly distinct architectures. To circumvent this limitation, a new exact-search alignment tool (BowMapCL) based on the Burrows-Wheeler Transform and FM-Index is presented. Contrasting to other alternatives, BowMapCL is based on a unified implementation using OpenCL, allowing the exploitation of multiple and possibly different devices (e.g., NVIDIA, AMD/ATI, and Intel GPUs/APUs). Furthermore, to efficiently exploit such heterogeneous architectures, BowMapCL incorporates several techniques to promote its performance and scalability, including multiple buffering, work-queue task-distribution, and dynamic load-balancing, together with index partitioning, bit-encoding, and sampling. When compared with state-of-the-art tools, the attained results showed that BowMapCL (using a single GPU) is 2 × to 7.5 × faster than mainstream multi-threaded CPU BWT-based aligners, like Bowtie, BWA, and SOAP2; and up to 4 × faster than the best performing state-of-the-art GPU implementations (namely, SOAP3 and HPG-BWT). When multiple and completely distinct devices are considered, BowMapCL efficiently scales the offered throughput, ensuring a convenient load-balance of the involved processing in the several distinct devices.

A GPU-Based Parallel Genetic Algorithm for Generating Daily Activity Plans

As computing technologies develop, there is a trend in traffic simulation research in which the focus is moving from macro- and meso-simulation to micro-simulation since micro-simulation can provide more detailed quantitative results. Moreover, the success of the Artificial societies-Computational experiments-Parallel execution (ACP) approach indicates that integrating other metropolitan systems such as logistic, infrastructure, legal and regulatory, and weather and environmental systems to build an Artificial Transportation System (ATS) can be helpful in solving Intelligent Transportation Systems (ITS) problems. However, the computational burden is very heavy as there are many agents interacting in parallel in the ATS. Therefore, a parallel computing tool is desirable. We think that we can employ a Graphics Processing Unit (GPU), which has been applied in many areas. In this paper, we use a GPU-adapted Parallel Genetic Algorithm (PGA) to solve the problem of generating daily activity plans for individual and household agents in the ATS, which is important as the activity plans determine the traffic demand in the ATS. Previous research has shown that GA is effective but that the computational burden is heavy. We extend the work to GPU and test our method on an NVIDIA Tesla C2050 GPU for two scenarios of generating plans for 1000 individual agents and 1000 three-person household agents. Speedup factors of 23 and 32 are obtained compared with implementations on a mainstream CPU.

Efficient parallel implementation of the lattice Boltzmann method on large clusters of graphic processing units

Many-core processors, such as graphic processing units (GPUs), are promising platforms for intrinsic parallel algorithms such as the lattice Boltzmann method (LBM). Although tremendous speedup has been obtained on a single GPU compared with mainstream CPUs, the performance of the LBM for multiple GPUs has not been studied extensively and systematically. In this article, we carry out LBM simulation on a GPU cluster with many nodes, each having multiple Fermi GPUs. Asynchronous execution with CUDA stream functions, OpenMP and non-blocking MPI communication are incorporated to improve efficiency. The algorithm is tested for two-dimensional Couette flow and the results are in good agreement with the analytical solution. For both the one- and two-dimensional decomposition of space, the algorithm performs well as most of the communication time is hidden. Direct numerical simulation of a two-dimensional gas-solid suspension containing more than one million solid particles and one billion gas lattice cells demonstrates the potential of this algorithm in large-scale engineering applications. The algorithm can be directly extended to the three-dimensional decomposition of space and other modeling methods including explicit grid-based methods.

Implementing wave propagation on desktop graphics processing units: Split-step Fourier parabolic equation modeling example.

The quest for raw computing power has shifted from increasing processor clock speeds to increasing the number of processing cores. Currently, mainstream CPUs can be purchased in dual-slot quad-core and hex-core configurations. On the other hand, graphic cards provide hundreds of processing cores. Although there have been various implementations of scientific applications on graphics hardware, including underwater acoustic modeling, widespread use of this technology has been hampered by the often extraordinary effort needed to program this hardware, especially if the application architecture did not match the canonical graphics pipeline for gaming. In the last few years, the major graphics board manufacturers have stepped away from designing hardware specialized for particular new graphic special effects and made a concerted effort to provide general-purpose computing capabilities, of the sort that can be exploited for scientific computing. For example, Nvidia’s CUDA environment currently provides many building blocks for scientific computing, such as (subsets of) BLAS, LAPACK, and FFTs. We will present our experiences implementing the split-step Fourier parabolic equation in the CUDA environment, showing how we have achieved a 10 times speedup relative to a multi-core CPU implementation, with a modest investment in programming effort. We will also provide some guidelines on how various applications of interest to the underwater acoustics community might benefit from use of this technology.

Direct numerical simulation of sub-grid structures in gas–solid flow—GPU implementation of macro-scale pseudo-particle modeling

Due to significant multi-scale heterogeneity, understanding sub-grid structures is critical to effective continuum-based description of gas–solid flow. However, it is challenging for both physical measurements and numerical simulations. In this article, with the macro-scale pseudo-particle method (MaPPM) implemented on a GPU-based HPC system, up to 30,000 fluidized solids are simulated using the N–S equation directly. The destabilization of uniform suspensions and the formation of solids clusters are reproduced in two-dimensional suspensions. Distinct scale-dependence of the statistical properties in the systems at moderate solid/gas density ratio is observed. Obvious cluster formation and its effect on drag coefficient are shown in a system at high solid/gas density ratio. On the computational side, about 19 folds speedup is obtained on one GT200 GPU, as compared to a mainstream CPU core. The necessity for investigating even larger systems is prospected.