Main Processing Element Research Articles

A predictor circuit and a delay-aware algorithm for identifying data transfer pattern on NoC-based communication networks

Deploying the Internet of Things and machine learning (ML)-based applications increased processing rate and data transfer between main memory and processing elements (PEs) in NoC-based communication networks, leading to memory access problems. Predicting and identifying reusable data for different tasks can reduce memory accesses and support various applications with high flexibility. Therefore, we propose a method to minimize memory access. It provides a predictor circuit to assign the address for PEs based on data buffering into task cores due to their reusability. We also present a delay-aware algorithm to investigate the initial relationship between tasks and identify a similar pattern for the mapped task graph on the various topologies. Our algorithm and predictor circuit decrease latency for determining related data to tasks and transfers data from global buffer onto PEs and buffers them according to its reusability for tasks with similar patterns. We utilized real data of the reported COVID-19 statistics and particulate matter 2.5 (PM2.5) condensation for evaluating our method. Simulation results demonstrate reducing energy consumption, delay, memory access, and increasing area consumption by approximately 61.83%, 39.96%, 66.66%, and 0.13%, respectively, for the mapped task graphs on a mesh network before employing the circuit and algorithm.

The Associative Memory System Infrastructures for the ATLAS Fast Tracker

The associative memory (AM) system of fast tracker (FTK) processor has been designed for the tracking trigger upgrade to the ATLAS detector at the Conseil Europeen Pour La Recherche Nucleaire large hadron collider. The system performs pattern matching (PM) using the detector hits of particles in the ATLAS silicon tracker. The AM system is the main processing element of FTK and is mainly based on the use of application-specified integrated circuits (ASICs) (AM chips) designed to execute PM with a high degree of parallelism. It finds track candidates at low resolution which become seeds for a full resolution track fitting. The AM system implementation is based on a collection of large 9U Versa Module Europa (VME) boards, named “serial link processors” (AMBSLPs). On these boards, a huge traffic of data is implemented on a network of 900 2-Gb/s serial links. The complete AM-based processor consumes much less power (~50 kW) than its CPU equivalent and its size is much smaller. The AMBSLP has a power consumption of ~250 W and there will be 16 of them in a crate. This results in unusually large power consumption for a VME crate and the need for complex custom infrastructure in order to have sufficient cooling. This paper reports on the design and testing of the infrastructures needed to run and cool the system which will include 16 AMBSLPs in the same crate, the integration of the AMBSLP inside a first FTK slice, the performance of the produced prototypes (both hardware and firmware), as well as their tests in the global FTK integration. This is an important milestone to be satisfied before the FTK production.

Digital Equalization for Cancellation of Noise-Like Interferences in Adaptive Spatial Filtering

Adaptive equalizer is an indispensable component of many radar systems for the cancellation of interference which arises due to mismatches in radar channels. This paper presents a reformulated LMS algorithm-based pipelined architecture of adaptive transversal equalizer that uses CORDIC as a main processing element to update angles instead of filter coefficients. In this architecture, hardware complexity has been reduced to a larger extent by utilizing pipeline method throughout the architecture. The lacuna of real-time system remains in the speed at which multiplication can be executed. We have proposed a modified version of pipelined Booth multiplier which uses partial product reduction scheme using 4---2 adder to reduce the computational time significantly. The hardware realization of the design reveals that critical path delay, area utilization and power consumption are reasonably low and therefore proposed design can be suitably be accommodated in modern-day radar system. The efficacy of the proposed interference canceller has been justified with extensive MATLAB simulations as well as hardware synthesis result for mitigation of interference in multi-channel radar systems.

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

This work presents the VLSI hardware implementation of a novel Belief Propagation (BP) algorithm introduced in [G. Montorsi, “Analog digital belief propagation,” IEEE Commun. Lett., vol. 16, no. 7, pp. 1106-1109, 2012] and named as Analog Digital Belief Propagation (ADBP). The ADBP algorithm works on factor graphs over linear models and uses messages in the form of Gaussian like probability distributions by tracking their parameters. In particular, ADBP can deal with system variables that are discrete and/or wrapped. A variant of ADBP can then be applied for the iterative decoding of a particular class of non binary codes and yields decoders with complexity independent of alphabet size M, thus allowing to construct efficient decoders for digital transmission systems with unbounded spectral efficiency. In this work, we propose some simplifications to the updating rules for ADBP algorithm that are suitable for hardware implementation. In addition, we analyze the effect of finite precision on the decoding performance of the algorithm. A careful selection of quantization scheme for input, output and intermediate variables allows us to construct a complete ADBP decoding architecture that performs close to the double precision implementation and shows a promising complexity for large values of M. Finally, synthesis results of the main processing elements of ADBP are reported for 45 nm standard cell ASIC technology.

Text image compression based on statistical analysis and classification of the vertical line elements

A new original method for text data image compression is presented. Vertical line elements rather than connecting symbols of the text image are used as the main processing element. The given probability model quite accurately describes possible distortions of the vertical line elements, caused by printing and scanning noise. Based on the accepted probability model and statistical analysis methods, minimum most plausible set of undistorted elements in the entire set of the investigated vertical line elements is found. For each vertical element, the probability that this element is a distortion of an element of the set of undistorted line elements is found. Classification of the vertical line elements of the text image is based on a probabilistic assessment of the classified elements belonging to a single center. The end result of the proposed method is forming a dictionary of connecting symbols of the text image, where each class is represented by its most probable image and an allocation map of connecting symbols on the plane of the studied image. The proposed text image processing method has allowed to obtain a relatively high compression ratio with good quality of the reconstructed image. Comparison with the currently best special text image compression algorithm - JB2, within the format DjVu, has shown that the proposed algorithm has the advantage in data compression ratio of about 37% in processing a text page image with a resolution of 300 dpi.

TRANSMISSION OF ARM BASED REAL TIME ECG FOR MONITORING REMOTELY LOCATED PATIENT

The development of patient monitoring system is of great importance in today’s stressed and busy world where people even don’t have time to visit doctors again and again. The need of instant medical help is also increasing day by day and can be achieved with wireless technology thereby motivating for wireless patient monitoring system. Also among all the diseases Cardiovascular is one that accounts for high mortality rate across the globe. So, the proposed system uses the key concept of wireless sensor network and focuses on ECG signal. This system relies on 3 lead ECG clamp to capture real time ECG of the patient and GSM/GPRS SIM300 module for real time wireless transmission. . Since, we are dealing with an important parameter that is ECG data integrity is must and is accomplished using TCP protocol. The main processing element used is ARM7 and ECG signal is efficiently received on PC in MATLAB at doctor workstation.

FAMOUS, faster: using parallel computing techniques to accelerate the FAMOUS/HadCM3 climate model with a focus on the radiative transfer algorithm

Abstract. We have optimised the atmospheric radiation algorithm of the FAMOUS climate model on several hardware platforms. The optimisation involved translating the Fortran code to C and restructuring the algorithm around the computation of a single air column. Instead of the existing MPI-based domain decomposition, we used a task queue and a thread pool to schedule the computation of individual columns on the available processors. Finally, four air columns are packed together in a single data structure and computed simultaneously using Single Instruction Multiple Data operations. The modified algorithm runs more than 50 times faster on the CELL's Synergistic Processing Element than on its main PowerPC processing element. On Intel-compatible processors, the new radiation code runs 4 times faster. On the tested graphics processor, using OpenCL, we find a speed-up of more than 2.5 times as compared to the original code on the main CPU. Because the radiation code takes more than 60 % of the total CPU time, FAMOUS executes more than twice as fast. Our version of the algorithm returns bit-wise identical results, which demonstrates the robustness of our approach. We estimate that this project required around two and a half man-years of work.

Methodology for Energy-Flexibility Space Exploration and Mapping of Multimedia Applications to Single-Processor Platform Styles

Embedded multimedia devices are now a common element of our environment, such as mp3 players, handheld devices, and so on. Choosing the right main processing element is a key issue for the success of these devices, and their consumption, performance, retargetability, and development time are some of the elements that need to be analyzed and well-balanced. In this paper, we map the same multimedia application (MPEG-4 main profile) into various target platforms generally used in the embedded area. The design flow of our work starts with a single MPEG-4 encoder description which is later refined and optimized to be implemented on different platforms: an embedded platform formed by a high performance digital signal processor and an embedded processor, an application specific instruction processor, a specific hardware implemented in a field-programmable gate array for accelerating the data-flow part of the system with a soft-core for the control part, and an application specific integrated circuit. The main contribution of this paper is to illustrate a methodology that can be generalized to different data dominant applications. This paper describes a new methodology to obtain near optimal implementation from concept to silicon for all platforms and it can be extended to any hybrid HW/SW multimedia platform. We evaluate the different transformations of each platform to arrive at an optimal implementation. These higher level transformations allow achieving better results than using more precise efforts in mapping the design in the physical level. This methodology can be extended to any data dominant application.

Sows’ activity classification device using acceleration data – A resource constrained approach

This paper discusses the main architectural alternatives and design decisions in order to implement a sows’ activity classification model on electronic devices. The different possibilities are analyzed in practical and technical aspects, focusing on the implementation metrics, like cost, performance, complexity and reliability. The target architectures are divided into: server based, where the main processing element is a central computer; and embedded based, where the processing is distributed on devices attached to the animals. The initial classification model identifies the activities performed by the sows using a multi-process Kalman filter having, as input, 3-axes data from accelerometers. However, the power demanding hardware resources to run the filters require frequent battery recharges, making its use unsuitable in the current state-of-the-art. It motivated the development of a heuristic classification approach, focusing on the resource constrained characteristics of embedded systems. The new approach classifies the activities performed by the sows with accuracy close to 90%. It was implemented as a hardware module that can easily be instantiated to provide preprocessed information to models in order to detect important situations in the sows’ life, e.g. the onset of farrowing.

Collaboration of reconfigurable processors in grid computing: Theory and application

Traditional grid networks employ General Purpose Processors (GPPs) as their main processing elements. Incorporating reconfigurable processing elements in such networks can be a promising technology to increase their performance. In this paper, we propose and simulate collaboration of reconfigurable processors in grid computing. Collaborative Reconfigurable Grid Computing (CRGC) employs the availability of any reconfigurable processor to accelerate compute-intensive applications such as multimedia kernels. We explore the mapping of some compute-intensive multimedia kernels such as the 2D DWT and the co-occurrence matrix in the CRGC. These multimedia kernels are simulated as an independent set of gridlets submitted to a software simulator called CRGridSim. In addition, we analyze the lower and upper bounds of performance for CRGC. Our experimental results show that the CRGC approach improves performance up to 7.2 × and 2.5 × compared to a single GPP and the collaboration of GPPs, respectively, when assuming a speedup of 10 of the reconfigurable processors in a grid with 4 nodes.

Feasibility of decoupling memory management from the execution pipeline

In conventional architectures, the central processing unit (CPU) spends a significant amount of execution time allocating and de-allocating memory. Efforts to improve memory management functions using custom allocators have led to only small improvements in performance. In this work, we test the feasibility of decoupling memory management functions from the main processing element to a separate memory management hardware. Such memory management hardware can reside on the same die as the CPU, in a memory controller or embedded within a DRAM chip. Using Simplescalar, we simulated our architecture and investigated the execution performance of various benchmarks selected from SPECInt2000, Olden and other memory intensive application suites. Hardware allocator reduced the execution time of applications by as much as 50%. In fact, the decoupled hardware results in a performance improvement even when we assume that both the hardware and software memory allocators require the same number of cycles. We attribute much of this improved performance to improved cache behavior since decoupling memory management functions reduces cache pollution caused by dynamic memory management software. We anticipate that even higher levels of performance can be achieved by using innovative hardware and software optimizations. We do not show any specific implementation for the memory management hardware. This paper only investigates the potential performance gains that can result from a hardware allocator.

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip

This paper presents a 2-D DCT/IDCT processor chip for high data rate image processing and video coding. It uses a fully pipelined row---column decomposition method based on two 1-D DCT processors and a transpose buffer based on D-type flip-flops with a double serial input/output data-flow. The proposed architecture allows the main processing elements and arithmetic units to operate in parallel at half the frequency of the data input rate. The main characteristics are: high throughput, parallel processing, reduced internal storage, and maximum efficiency in computational elements. The processor has been implemented using standard cell design methodology in 0.35 ?m CMOS technology. It measures 6.25 mm2 (the core is 3 mm2) and contains a total of 11.7 k gates. The maximum frequency is 300 MHz with a latency of 172 cycles for 2-D DCT and 178 cycles for 2-D IDCT. The computing time of a block is close to 580 ns. It has been designed to meets the demands of IEEE Std. 1,180---1,990 used in different video codecs. The good performance in the computing speed and hardware cost indicate that this processor is suitable for HDTV applications.

A guide to migrating from microprocessor to FPGA coping with the support tool limitations

Microprocessors have been used as the main processing elements of embedded systems mainly because of their low cost, flexibility for system upgrade at the software level and because of the availability of efficient support tools. The configurable computing technology brought the software flexibility to the hardware level, but limitations in support tools are a barrier for software designers. Using a microcontroller based embedded system as a study case, this paper introduces workable strategies to be used by software designers to develop a complete embedded system (software+hardware parts) using a single description language, and circumventing support tool limitations.

A bit-serial first-level calorimeter trigger for an LHC detector

A preliminary design of a compact first-level calorimeter trigger, implemented as a farm of local bit-serial systolic arrays, is presented. The bit-serial data representation allows higher processing rates and more compact designs than are possible when using parallel data. More functionality can be incorporated into the Application Specific Integrated Circuits (ASICs) that serve as the main processing elements. The trigger processor seeks local energy clusters, evaluates isolation criteria within the electromagnetic calorimeter and leakage into the hadron calorimeter in order to detect electrons. It uses cluster finding algorithms to identify jets and missing transverse energy to estimate neutrino energies. The processor output serves as decision support for the central first-level trigger and delivers region-of-interest positions to the second-level trigger. In its present form the trigger processor design relies on optical fibers to deliver the input data from the front-end modules and multi-chip modules (MCMs) to harbor the processing ASICs. The fact that the main part of the trigger processor can fit into one or two large crates suggests that the design is not limited by size nor is it strictly limited by cost but can be expanded to accommodate extended algorithms if these are found necessary. Extensive physics simulations will explore these possibilities.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Logic programs directly processed in a network of content addressable memories

A task-oriented controller to manage learning robots was described in Callataÿ (1986). The main processing element is a phasic categorizer, the output of which is an instantiated symbol transmitted to many other categorizers. Categorizers are the nodes of a directed circular network processor system (DNPS). The impulses (instantiated symbols) concurrently flow within the DNPS loops. The system is radically different from conventional computers and parallel processors. Memory consists of relationships which are stored in the processing elements: these are “recording content addressable memories” (RCAM) which can do only one machine instruction type: “association for production rule processing”. A well-designed DNPS can resolve complex problems, like some rule based or logic programs. Predicates do not appear in the compiled programs. They are replaced by instantiable keywords. Production rules are represented like documents described with keywords and are processed by an information retrieval algorithm. Processing may continue even when no rule matches because analogies may be discovered by partial matching and produce a relevant pseudo-logical solution from incomplete knowledge. The active working memory is matched in parallel with the whole rule base. The DNPS controller is suggested as the central part of a brain model.

Implementation of a 64-point adaptive filter using an analogue c.c.d. programmable filter

This letter describes the construction and operation of an adaptive filter based on the Widrow least-mean-square adaption algorithm using a 64-point analogue programmable c.c.d. transversal filter as the main processing element. Initial test results are presented to confirm the principle of the system and these results may be readily compared with previously published simulation results.