Main Memory Systems Research Articles

Inkjet‐Printed Phase Change Memory Devices

AbstractPhase change memory (PCM) is among the most promising candidates for the next generation of storage‐class and main memory systems in the computing era beyond Moore's law. However, the widespread installment of PCM devices is limited by the high price‐per‐bit and complex fabrication process. In this paper, it is shown that functional PCM memory devices can be printed, proving low‐cost avenues for non‐silicon memory technologies. Taking Ge‐Sb‐Te (GST) as a case study, PCM inks are prepared and optimize their structural, rheological, and printing parameters. GST layers are then printed onto PCM devices in the planar configuration, showing excellent performance, such as non‐volatility, resistivity contrast, low cycle‐to‐cycle variability, and endurance of at least 100 cycles. This paper provides a novel approach to liquid‐based engineered PCM devices through inkjet printing, enabling patterned memory layers, lower price‐per‐bit, and customizable multi‐material PCM arrays.

RTIndeX: Exploiting Hardware-Accelerated GPU Raytracing for Database Indexing

Data management on GPUs has become increasingly relevant due to a tremendous rise in processing power and available GPU memory. Similar to main-memory systems, there is a need for performant GPU-resident index structures to speed up query processing. Unfortunately, mapping indexes efficiently to the highly parallel and hard-to-program hardware is challenging and often fails to yield the desired performance and flexibility. Instead of proposing yet another hand-tailored index, we investigate whether we can exploit an indexing mechanism that is already built into modern GPUs: The raytracing hardware accelerator provided by NVIDIA RTX GPUs. To do so, we re-phrase the database indexing problem as a raytracing problem, where we express the dataset to be indexed as objects in a 3D scene, and point/range lookups as rays across the scene. In this combination, coined RX in the following, lookups are performed as intersection tests in hardware by dedicated raytracing cores. To analyze the pros, cons, and usefulness of the raytracing pipeline for database indexing, we carefully evaluate RX along fourteen dimensions and demonstrate its competitiveness and potential in a large variety of situations.

Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories

Main memory system design and corresponding technology requirements have become increasingly challenging for data-dominated high-performance applications. To address the leakage and scalability issues of the conventional DRAM-based memory, new memory technologies with ultra-low leakage and potential for high scalability have been explored extensively over the last decade. However, none of them are mature enough to serve as a drop-in replacement for DRAM. In this paper, we propose a hybrid main memory system solution for utilizing new memory technologies with specific features, based on the target application characteristics and system configurations. To this end, we examine two new memories, 1S-1VCMA and IGZO-based DRAM, along with conventional DRAM in the context of hybrid main memory solutions for high-capacity and low-power Pareto-optimizations, respectively. To better evaluate the power and performance, we consider the page-fault modeling in our evaluations. The results of the simulation show that different combinations of memory technologies in the hybrid memory system, different memory capacities, and different storage systems could provide a promising solution in the system regarding the characteristics of running applications and the requirements of the system.

Attentional distraction affects maintenance of information in visual sensory memory

Classical theoretical models suggest that visual short-term memory can be divided in two main memory systems: sensory memory, a short-lasting but high-capacity memory storage and working memory, a long-lasting but low-capacity memory store. Whilst, previous research has systematically shown a strong interplay between attentional mechanisms and working memory, less clear is the role of attention in sensory memory. In the present study we approach this issue by asking whether withdrawing attentional resources by a dual task (Experiment 1) or by presenting task irrelevant information during memory maintenance (Experiment 2 and 3) similarly or differently affect sensory and working memory. Overall, results showed that sensory memory content was undermined not only by a simultaneous high-demanding cognitive task but even when purely task-irrelevant and non-masking visual distractors were presented during maintenance. Our data provide support against theories that consider sensory memories as a case of visual awareness free of attention.

Architecting Optically Controlled Phase Change Memory

Phase Change Memory (PCM) is an attractive candidate for main memory, as it offers non-volatility and zero leakage power while providing higher cell densities, longer data retention time, and higher capacity scaling compared to DRAM. In PCM, data is stored in the crystalline or amorphous state of the phase change material. The typical electrically controlled PCM (EPCM), however, suffers from longer write latency and higher write energy compared to DRAM and limited multi-level cell (MLC) capacities. These challenges limit the performance of data-intensive applications running on computing systems with EPCMs. Recently, researchers demonstrated optically controlled PCM (OPCM) cells with support for 5 bits / cell in contrast to 2 bits / cell in EPCM. These OPCM cells can be accessed directly with optical signals that are multiplexed in high-bandwidth-density silicon-photonic links. The higher MLC capacity in OPCM and the direct cell access using optical signals enable an increased read/write throughput and lower energy per access than EPCM. However, due to the direct cell access using optical signals, OPCM systems cannot be designed using conventional memory architecture. We need a complete redesign of the memory architecture that is tailored to the properties of OPCM technology. This article presents the design of a unified network and main memory system called COSMOS that combines OPCM and silicon-photonic links to achieve high memory throughput. COSMOS is composed of a hierarchical multi-banked OPCM array with novel read and write access protocols. COSMOS uses an Electrical-Optical-Electrical (E-O-E) control unit to map standard DRAM read/write commands (sent in electrical domain) from the memory controller on to optical signals that access the OPCM cells. Our evaluation of a 2.5D-integrated system containing a processor and COSMOS demonstrates 2.14 × average speedup across graph and HPC workloads compared to an EPCM system. COSMOS consumes 3.8× lower read energy-per-bit and 5.97× lower write energy-per-bit compared to EPCM. COSMOS is the first non-volatile memory that provides comparable performance and energy consumption as DDR5 in addition to increased bit density, higher area efficiency, and improved scalability.

An Adaptive Memory-Side Encryption Method for Improving Security and Lifetime of PCM-Based Main Memory

In this article, we present a main memory system for improving the lifetime and security of phase-change main memories. Storing encrypted data increases the bit-flip rates in memory cells, which adversely affects the lifetime of the phase-change memory cells. Thus, to improve the lifetime and security, the proposed system reduces the bit-flip rates by introducing two techniques. The first technique is a memory-side encryption which provides security against DIMM stealing attacks. To prevent unauthorized accesses, in this technique, the encrypted data are not saved in the main memory. As the second technique, we suggest an adaptive partial encryption approach, which makes use of behavior tracking of the application in the CPU side to minimize the latency overhead of the first technique. Additionally, it prevents the loss of data against application-based attacks. This technique uses a recurrent neural network (RNN) to do sequence classification and detect malicious applications. In addition, an auxiliary method, called periodic encryption (PE), which overcomes the security loss in some applications induced by the low accuracy of the employed neural network, is presented. The efficacy of the proposed method is evaluated using gem5 simulator and some benchmarks. Compared to DEUCE and Crypto-Comp methods, the results for the lifetime evaluation show an average bit-flip rate reduction of 11%. In addition, the security improvements against the DIMM stealing and application-based attacks are about 100% and 92.5%, respectively.

A prospective behavioral and imaging study exploring the impact on long-term memory of radiotherapy delivered for a brain tumor in childhood and adolescence

BackgroundPosterior fossa tumors represent two thirds of brain tumors in children. Although progress in treatment has improved survival rates over the past few years, long-term memory impairments in survivors are frequent and have an impact on academic achievement. The hippocampi, cerebellum and cerebellar-cortical networks play a role in several memory systems. They are affected not only by the location of the tumor itself and its surgical removal, but also by the supratentorial effects of complementary treatments, particularly radiotherapy. The IMPALA study will investigate the impact of irradiation doses on brain structures involved in memory, especially the hippocampi and cerebellum. Methods/designIn this single-center prospective behavioral and neuro-imaging study, 90 participants will be enrolled in three groups. The first two groups will include patients who underwent surgery for a posterior fossa brain tumor in childhood, who are considered to be cured, and who completed treatment at least 5 years earlier, either with radiotherapy (aggressive brain tumor; Group 1) or without (low-grade brain tumor; Group 2). Group 3 will include control participants matched with Group 1 for age, sex, and handedness. All participants will perform an extensive battery of neuropsychological tests, including an assessment of the main memory systems, and undergo multimodal 3 T MRI. The irradiation dose to the different brain structures involved in memory will be collected from the initial radiotherapy dosimetry. DiscussionThis study will provide long-term neuropsychological data about four different memory systems (working memory, episodic memory, semantic memory, and procedural memory) and the cognitive functions (attention, language, executive functions) that can interfere with them, in order to better characterize memory deficits among the survivors of brain tumors. We will investigate the correlations between neuropsychological and neuroimaging data on the structural (3DT1), microstructural (DTI), functional (rs-fMRI), vascular (ASL) and metabolic (spectroscopy) impact of the tumor and irradiation dose. This study will thus inform the setting of dose constraints to spare regions linked to the development of cognitive and memory functions. Trial registrationClinicalTrials.gov: NCT04324450, registered March 27, 2020, updated January 25th, 2021. Retrospectively registered, https://www.clinicaltrials.gov/ct2/show/NCT04324450.

Current and Upcoming Challenges of the Main Memory System (2021)

Current and Upcoming Challenges of the Main Memory System (2021)

Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System

This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.

Storage Class Memory Based Hybrid Memory System for Practical Remote Sensing

Koo, S.M.; Seo, J.M.; Song. Y.J., and Baek, S.J., 2020. Storage class memory based hybrid memory system for practical remote sensing. In: Jung, H.-S.; Lee, S., and Ryu, J.-H. (eds.), In: Jung, H.-S.; Lee, S.; Ryu, J.-H., and Cui, T. (eds.), Advances in Geospatial Research of Coastal Environments. Journal of Coastal Research, Special Issue No. 102, pp. 254-260. Coconut Creek (Florida), ISSN 0749-0208.In the remote sensing domain, large-sized, files such as high-resolution satellite images or sonar video clips from unmanned underwater vehicles are very common. For processing big files, a large main memory is necessary. The main memory capacity highly influences the performance of computer systems. The demand for DRAM capacity has never been satisfied, and more importantly, large DRAM systems suffer from significant power consumption. To ease the problem, a promising solution is to build a hybrid main memory (HMM) system composed of a small number of fast DRAMs and many inexpensive devices. By mimicking large and fast main memory capacity, HMM allows computer systems to run applications that require more DRAM than is installed on the system. In this paper, a novel HMM management scheme for a storage class memory (SCM)-based HMM was introduced. As all the data stored on SCM are already non-volatile, the overall performance of the computer system is enhanced further by not flushing them periodically. The proposed idea was implemented on Linux and its performance was measured using an SCM emulation system. It was shown that HMM efficiently improves performance by up to 77.9 %, compared with a conventional operating system. Additionally, it was demonstrated that the proposed idea's fault recovery mechanisms could restore dirty data that are not yet synchronized with storage, within 91 % of the test time.

Fileless malware and programmatic method of detection

Fileless malware lives unnoticeably in a computer system's main memory and executes its malicious processes freely. Although the anti-malware industry knows about this sophisticated form of attack ...

Access pattern-based high-performance main memory system for graph processing on single machines

With the increasing complexity of graph structures, the current real-world large-scale graphs are being represented by a considerable amount of vertex and edge data. Furthermore, the analysis of a large number of computing nodes has become a very complicated job that requires a large amount of hardware resources. Moreover, in large-scale graph processing, the vertex and edge data show random and sequential memory access patterns at the same time, and this is a major bottleneck in graph processing. In this paper, we present a high-capacity main memory system with an intelligent pattern-aware prefetching engine to overcome the scalability problem and the memory inefficiency of single-machine graph processing. The proposed intelligent pattern-aware prefetching engine is designed to predict and handle sequential or regular patterns and random-access patterns simultaneously. Experimental results demonstrated that the proposed model exhibited performance improvements of 60% over conventional DRAM models, approximately 40% over the existing prefetch models, and about 12.5% over the latest prefetch models.

Dapper: An Adaptive Manager for Large-Capacity Persistent Memory

Smart applications are becoming more data centric, and the need for businesses to quickly manage vast amounts of data continues to challenge today’s computing infrastructure. Nevertheless, main memory systems consisting entirely of dynamic random-access memory (DRAM) are already hitting their power and capacity limits. It would be beneficial to unleash significant system performance combined emerging memory modules without being worried about design complexities. Design innovations in highly scalable hybrid memory systems hold great promise to realize this vision.

Chapter 17 - Memory: Normative development of memory systems

During the past decades, abundant behavioral, clinical, and neuroimaging data have shown several memory systems in the brain. A memory system is a type of memory that processes a particular type of information, using specific mechanisms, with distinct neural correlates. What we call memory is therefore not a unitary capacity but a collection of distinct systems. From a developmental perspective, each memory system has its own developmental course. This explains the heterogeneity of children's mnemonic competencies: for example, 3-year-olds learn many new words and concepts every day but have trouble recalling in detail an event that happened the week before. In this chapter, we sum up major findings regarding the development from infancy to early adulthood of the main memory systems. Specifically, we report recent data regarding the development of declarative memory (i.e., episodic and semantic memory), and the relationship between the maturation of their neural correlates and the phenomena of infantile and childhood amnesia. We conclude by indicating some of the possible avenues for future research.

Optimizing Heap Memory Object Placement in the Hybrid Memory System With Energy Constraints

Main memory significantly impacts the power and energy utilization of the overall server system. Non-Volatile Memory (NVM) devices, are suitable candidates for the main memory to reduce static energy consumption. But unlike DRAM, the access latencies and the dynamic energy consumption of write operation of the NVM devices are higher. Thus, Hybrid Main Memory Systems (HMMS) employing DRAM and NVM have been proposed to reduce the overall energy depletion of main memory while optimizing the performance of application. However, memory object placement is crucial for optimal performance and energy efficiency in HMMS due to high write latency and energy consumption of NVM devices. This paper proposes eMap, an optimal heap memory object placement planner for HMMS. eMap takes into account the object-level access patterns and energy consumption to provide an ideal placement policy for objects to mitigate performance and energy consumption. In particular, eMap is equipped with two modules, eMPlan and eMDyn. eMPlan is a static placement planner which provides one-time placement policies for memory objects to meet the energy budget. eMDyn is a runtime model to consider the requests of changes in the energy constraint during the application execution. Both modules are based in Integer Linear Programming(ILP) and consider three major constraints, namely decision, capacity and energy constraints to optimally placing the memory objects in HMMS. We evaluate the proposed solution with two scientific application benchmarks, NAS Parallel Benchmark (NPB) and Problem-based Benchmark Suit (PBBS), on two testbeds by emulating the NVM using QUARTZ [32]. Our extensive experiments in comparison with Memory Object Classification and Allocation (MOCA) framework showed that our solution is 4.17 × less costly in terms of the memory object profiling and reduce the energy consumption up to 14% with the same performance. On the other hand, eMDyn module also meets the performance and energy requirement during the application execution by considering the migration cost in terms of time and energy.

Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die

Nonvolatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU's die. ReRAM bitcells are fabricated within crosspoint subarrays that leave the bulk of transistors underneath the subarrays vacant. This permits placing the memory system over the CPU, improving area, parallelism, and power. Our work quantifies the impact of integrating ReRAM into a CPU's die. When integrating ReRAM over CPU logic, the best area efficiency occurs when 48% of the die is covered with ReRAM. The CPU's area increases by 18.8%, but we can recoup 35.5% of the die area by utilizing the free transistors underneath the crosspoint subarrays. When integrating ReRAM over CPU cache, up to 85.3% of the cache can be covered with ReRAM. Our work also shows that on-die ReRAM can support very high bandwidth through massively parallel memory access. At 28 nm, 4–16k independent ReRAM banks could be integrated onto the CPU die, providing 512–1024–GB/s peak bandwidth. At more advanced technology nodes, 5–10 TB/s may be possible.

RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory

In this article, we present a simple, yet energy- and area-efficient method for tolerating the stuck-at faults caused by an endurance issue in secure-resistive main memories. In the proposed method, by employing the random characteristics of the encrypted data encoded by the Advanced Encryption Standard (AES) as well as a rotational shift operation, a large number of memory locations with stuck-at faults could be employed for correctly storing the data. Due to the simple hardware implementation of the proposed method, its energy consumption is considerably smaller than that of other recently proposed methods. The technique may be employed along with other error correction methods, including the error correction code (ECC) and the error correction pointer (ECP). To assess the efficacy of the proposed method, it is implemented in a phase-change memory (PCM)-based main memory system and compared with three error tolerating methods. The results reveal that for a stuck-at fault occurrence rate of 10−2 and with the uncorrected bit error rate of ${2 \times 10}^{-3}$ , the proposed method achieves 82% energy reduction compared to the state-of-the-art method. More generally, using a simulation analysis technique, we show that the fault coverage of the proposed method is similar to that of the state-of-the-art method.

Exploiting OS-Level Memory Offlining for DRAM Power Management

Power and energy consumed by main memory systems in data-center servers have increased as the DRAM capacity and bandwidth increase. Particularly, background power accounts for a considerable fraction of the total DRAM power consumption; the fraction will increase further in the near future, especially when slowing-down technology scaling forces us to provide necessary DRAM capacity through plugging in more DRAM modules or stacking more DRAM chips in a DRAM package. Although current DRAM architecture supports low power states at rank granularity that turn off some components during idle periods, techniques to exploit memory-level parallelism make the rank-granularity power state become ineffective. Furthermore, the long wake-up latency is one of obstacles to adopting aggressive power management (PM) with deep power-down states. By tackling the limitations, we propose OffDIMM that is a software-assisted DRAM PM collaborating with the OS-level memory onlining/offlining. OffDIMM maps a memory block in the address space of the OS to a subarray group or groups of DRAM, and sets a deep power-down state for the subarray group when offlining the block. Through the dynamic OS-level memory onlining/offlining based on the current memory usage, our experimental results show OffDIMM reduces background power by 24 percent on average without notable performance overheads.

Level Hashing

Non-volatile memory (NVM) technologies as persistent memory are promising candidates to complement or replace DRAM for building future memory systems, due to having the advantages of high density, low power, and non-volatility. In main memory systems, hashing index structures are fundamental building blocks to provide fast query responses. However, hashing index structures originally designed for dynamic random access memory (DRAM) become inefficient for persistent memory due to new challenges including hardware limitations of NVM and the requirement of data consistency. To address these challenges, this article proposes level hashing , a write-optimized and high-performance hashing index scheme with low-overhead consistency guarantee and cost-efficient resizing. Level hashing provides a sharing-based two-level hash table, which achieves constant-scale worst-case time complexity for search, insertion, deletion, and update operations, and rarely incurs extra NVM writes. To guarantee the consistency with low overhead, level hashing leverages log-free consistency schemes for deletion, insertion, and resizing operations, and an opportunistic log-free scheme for update operation. To cost-efficiently resize this hash table, level hashing leverages an in-place resizing scheme that only needs to rehash 1/3 of buckets instead of the entire table to expand a hash table and rehash 2/3 of buckets to shrink a hash table, thus significantly improving the resizing performance and reducing the number of rehashed buckets. Extensive experimental results show that the level hashing speeds up insertions by 1.4×−3.0×, updates by 1.2×−2.1×, expanding by over 4.3×, and shrinking by over 1.4× while maintaining high search and deletion performance compared with start-of-the-art hashing schemes.

Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory

As the number of datasets processed in computing systems has increased in recent years, there is growing demand for high capacity main memory subsystems. However, further increases in the capacity of conventional DRAM-based main memory systems have stalled due to scaling limitations. Recent studies have shown that PCM, which can provide greater capacity than DRAM, is emerging as a candidate for high capacity memory. However, PCM suffers from problems related to the thermal mechanisms employed for storing data. The Write Disturbance (WD) phenomenon occurs when the thermal mechanisms of the PCM severely damage the data reliability of proximate cells. WD in PCM has become more significant below 20 nm. In this paper, we propose Sparse-Insertion Write Cache (SIWC), a practical, low-cost approach to mitigate WD errors. In PCM, repeated writes gradually degrade the validity of data in neighboring cells. SIWC uses a private write cache for the PCM write data to prevent repeated writes to the same address. The sparse-insertion technique can reduce cache eviction and minimize increases in the total write count. Our experimental results show that SIWC effectively reduces repeated writes and reduces the number of WD-vulnerable addresses across a wide range of applications.