Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System

Jeong-Geun Kim,Su-Kyung Yoon,Shin-Dug Kim

doi:10.3390/electronics9122158

Jeong-Geun Kim, Su-Kyung Yoon + Show 1 more

Open Access

https://doi.org/10.3390/electronics9122158

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Journal: Electronics	Publication Date: Dec 16, 2020
Citations: 1	License type: CC BY 4.0

Affiliation: Yonsei University, Jeonbuk National University

Abstract

This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.

Highlights

In the in-memory computing and big-data processing era, computing systems are suffering from a lack of main memory capacity
dynamic random-access memory (DRAM) only: a baseline configuration based on conventional DDR4-DRAM main memory, Phase-change memory (PCM) only: a baseline configuration based on DDR4-PCM main memory without DRAM devices, DRAM/PCM hybrid memory system: a hybrid main memory-based system based on DRAM/non-volatile memory (NVM)
We observed that our proposed model achieves 25.8%, 37.6%, and 21.1% better IPC compared to the PCM only, the hybrid main memory system without prefetcher, and with access map pattern matching (AMPM) prefetcher, respectively

Summary

Introduction

In the in-memory computing and big-data processing era, computing systems are suffering from a lack of main memory capacity. Its limitation of scaling and high cost keeps the memory space smaller than the working set size required by modern applications To mitigate this problem, there have been several studies about how to apply new memory technologies into the system. Phase-change memory (PCM) is one of the most promising memory technologies, exhibiting high density, DRAM-comparable speed, and high cost-efficiency among the emerging memory candidates [1,2] Despite these advantages, the PCM cannot entirely replace DRAM devices because of its longer access latency (~3 × that of DRAM). The physical limitations of DRAM (e.g., scaling problem, refresh operation, etc.) technology act like a non-trivial obstacle to expand the size of the main memory layer To overcome these limitations of DRAM, many computer architects have introduced emerging memory technologies for computer architecture. These emerging memory devices are called non-volatile memory (NVM) or storage class memory (SCM) because of their nonvolatility characteristics like storage device and storage-class capacity with DRAM-comparable latency

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