Magnetoresistive Memory Research Articles

Dynamic switching process of sandwich-structured MR elements

The dynamic behavior of sandwich-structured magnetoresistive (MR) memory elements is studied analytically by solving Gilbert's equation together with the one-dimensional micromagnetic torque equation. The typical element is 2 mu m*20 mu m and consists of two 150-AA thick magnetic layers separated by a 50-AA thick nonmagnetic layer. The easy axis is along the short dimension of the element. The theoretical study shows that wall nucleation is present when the switching is driven by a field applied in the easy-axis direction, whereas switching by a field in the hard-axis direction is accomplished by coherent rotation. The switching speed predicted by this one-dimensional model is in the nanosecond range and increases linearly with the external fields. >

Analysis of M-R elements for 10/sup 8/ bit/cm/sup 2/ arrays

Magnetoresistive memory elements made from 100-AA thick, 65% Ni, 15% Fe, 20% Co layers separated by a 40-AA nonmagnetic layer have been analyzed theoretically. The analysis shows that with lithography capable of a minimum feature size of 0.4 mu m and with the ability to deposit nonconducting magnetic keepers, memory arrays with a density of 10/sup 8/ bit/cm/sup 2/ can be achieved. Analysis shows that such elements can lead to random access memories with an access time of 5 mu s. In the case of plated conducting keepers, the element density is slightly diminished. >

Thermal noise limitations to 2×20-μm2 magnetoresistive memory element thresholds

The effect of thermal agitation on the abruptness of the switching threshold for transverse magnetoresistive memory elements was examined. When the switching fields were within 1% or 2% of the threshold, thermal effects were observed.

The design of a one megabit non-volatile M-R memory chip using 1.5*5 mu m cells

A 10/sup 6/-bit chip has been designed using 1.5- mu m magnetoresistive double-layer memory elements and bipolar circuitry. The bipolar circuitry is based on nominal 1.25- mu m optical lithography. The total chip area of the design is 8.5 mm*9.5 mm. To enhance the signal-to-noise ratio, multiple reads are used with the nondestructive readout cells. Design read time is 3 mu s. Design write time is 0.2 mu s. The design includes three redundant, fuse-selectable sense lines for each group of 32 sense lines. If the bit failure rate is 0.0005 or less, yield loss for the 10/sup 6/-bit chip due to sense line failure is less than 19%. With improved lithography, elements as small as 0.75 mu m*2.5 mu m could be made from the material.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>