Magnetologic Gate Research Articles

MGate: A Universal Magnetologic Gate for Design of Energy Efficient Digital Circuits

This paper presents a universal magnetologic gate, the so-called magnetogate (mGate) for the design of energy efficient digital circuits. The mGate employs magnetic tunnel junction (MTJ) cells, which have valuable features such as non-volatility, lower power consumption, and higher integration density compared with transistor-based gates. mGate can be efficiently exploited to the design of different combinational and sequential logic circuits. HSPICE-based simulations have been carried out to verify the correct functionality of different mGate-based circuits. The simulation results reveal that the mGate provides low area, power consumption, and energy while also offering more flexibility as compared with previously proposed MTJ-based designs.

Spin-Hall Voltage over a Large Length Scale in Bulk Germanium.

We exploit the spin-Hall effect to generate a uniform pure spin current in an epitaxial n-doped Ge channel, and we detect the electrically induced spin accumulation, transverse to the injected charge current density, with polar magneto-optical Kerr microscopy at a low temperature. We show that a large spin density up to 400 μm^{-3} can be achieved at the edges of the 100-μm-wide Ge channel for an applied electric field lower than 5 mV/μm. We find that the spin density linearly decreases toward the center of the Ge bar, due to the large spin diffusion length, and such a decay is much slower than the exponential one observed in III-V semiconductors, allowing very large spin accumulations over a length scale of tens of micrometers. This lays the foundation for multiterminal spintronic devices, where different spin voltages can be exploited as inputs for magnetologic gates on the same Ge platform.

Experimental Demonstration of xor Operation in Graphene Magnetologic Gates at Room Temperature

We report the experimental demonstration of a magnetologic gate built on graphene at room temperature. This magnetologic gate consists of three ferromagnetic electrodes contacting a single layer graphene spin channel and relies on spin injection and spin transport in the graphene. We utilize electrical bias tuning of spin injection to balance the inputs and achieve "exclusive or" (XOR) logic operation. Furthermore, simulation of the device performance shows that substantial improvement towards spintronic applications can be achieved by optimizing device parameters such as device dimensions. This advance holds promise as a basic building block for spin-based information processing.

Spin-Transfer-Torque driven magneto-logic OR, AND and NOT gates

We show that current induced magneto-logic gates like AND, OR and NOT can be designed with the simple architecture involving a single nano spin-valve pillar, as an extension of our recent work on spin-torque-driven magneto-logic universal gates, NAND and NOR. Here the logical operation is induced by spin-polarized currents which also form the logical inputs. The operation is facilitated by the simultaneous presence of a constant controlling magnetic field, in the absence of which the same element operates as a magnetoresistive memory element. We construct the relevant phase space diagrams for the free layer magnetization dynamics in the monodomain approximation and show the rationale and functioning of the proposed gates. The flipping time for the logical states of these non-universal gates is estimated to be within nano seconds, just like their universal counter parts.

Multiple Extraction Spin Valves for Spintronic Circuits

The application of an electrical forward bias across a ferromagnet/semiconductor Schottky barrier can result in a non-equilibrium spin accumulation in the semiconductor. This mechanism is referred to as spin extraction. Like spin injection, spin extraction can also serve to generate the electron spin polarization, which is necessary for the operation of a local spin valve, i.e., a magnetoresistance device consisting of a ferromagnetic/non-magnetic/ferromagnetic hybrid structure, which exhibits an electrical resistance that depends on the relative orientation of the magnetizations of the two ferromagnetic electrodes. In such a spin extraction spin valve (SESV), a spin-polarized drift current is generated in a non-magnetic channel by spin extraction at a ferromagnetic electrode. The spin polarization influences the output current through a subsequent ferromagnetic electrode. We show how spin valve devices relying on multiple spin extraction events can be used for magneto-logic gate operation. Furthermore, we investigate the potential use of these structures as sources of highly spin-polarized drift currents.

Nanospintronics Based on Magnetologic Gates

We present a seamless integration of spin-based memory and logic circuits. The building blocks are magnetologic gates based on a hybrid graphene/ferromagnet material system. We use network search engines as a technology demonstration vehicle and simulate a high-speed, small-area, and low-power spin-based circuit.

Reconfigurable magnetologic computing using the spin flop switching of a magnetic random access memory cell

Today’s computers rely on dissipative logic gates that are based on transistors. Increasing computational power means increasing the integration density and power dissipation. Among other alternatives, utilization of magnetism is a promising approach. Based on recent developments for improving the technology for magnetic random access memory (MRAM), a concept is proposed of how to utilize forthcoming generations of MRAM chips in the spin flop switching mode as versatile reconfigurable magnetologic gate arrays. A single MRAM cell can be directly operated as either NOT, AND, or NAND gates, and the use of bipolar current makes XOR and XNOR feasible as well. The actual functionality can be pre-programmed at run-time and the output is nonvolatile. Based on the spin flop switching mode, this concept is directly applicable to second-generation MRAMs.