Magnetic Random Access Memory Cell Research Articles

Reconfigured Self-Referenced MRAM Cell Supporting 2.527-fJ/bit Reading and In Situ Multiplication

The development of nonvolatile memories (NVM) based normally-off, instantly-on applications is hindered by high energy consumption for data readout. In particular, magnetic random access memory (MRAM) is a promising candidate for embedded non-volatile memory for its high cell density, high endurance and compatibility with the CMOS process. However, considering the low tunneling magnetoresistance ratio (TMR) of standard 1T1MTJ bit-cell, the state-of-art voltage sensing amplifiers (VSA) and current sensing amplifiers (CSA) need the direct current path to build considerable voltage or current difference. This paper demonstrates a reconfigured latch-based 4T2MTJ bit-cell achieving 2.527-fJ/bit ultra-low-power data readout at 0.4-V read voltage. Simulated results show that 2-ns latency can be realized with a traditional VSA and parasitic capacitance. The proposed 4T2MTJ bit-cell can perform in-situation (in-situ) multiplication between stored data and input with negligible extra energy consumption.

Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance

This brief proposes a compact spin-orbit torque magnetic random-access memory (SOT-MRAM) cell structure with high read performance for embedded nonvolatile memory (eNVM) applications. The memory cell is composed of one transistor, two Schottky diodes, two magnetic tunnel junctions (MTJs) and one shared heavy metal (HM) layer, which can be abbreviated as 1T-2D-2MTJ cell. The two MTJs are stacked on the same HM layer for smaller area overhead and configured to be complementary with the magnetization of their pinned layers in the opposite direction to double the read sense margin. The write operation is also simplified since a current through the HM layer changes the resistances of both MTJs simultaneously. The evaluations include the micromagnetic simulation of the SOT device, the analysis of PVT variations for the read operation on bit-cell level, the estimation of bit-cell area and the simulations of performance and power consumption on array level. The results show that the proposed SOT-MRAM improves the performance and reliability of the read operation and achieves 75% (50%) reduction in bit-cell area compared to 4T-2MTJ SOT-MRAM (2T-2MTJ STT-MRAM), 83.0% reduction in write power consumption and 91.1% reduction in write latency compared to 2T-2MTJ STT-MRAM.

Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing

This brief deals with the impact of spin-transfer torque magnetic random access memory (STT-MRAM) cell based on double-barrier magnetic tunnel junction (DMTJ) on the performance of a two-layer multilayer perceptron (MLP) neural network. The DMTJ-based cell is benchmarked against the conventional single-barrier MTJ (SMTJ) counterpart by means of a comprehensive evaluation carried out through a state-of-the-art device-to-algorithm simulation framework. The benchmark is based on the MNIST handwritten dataset, Verilog-A MTJ compact models developed by our group, and 0.8 V FinFET technology. Our results point out that the use of DMTJ-based STT-MRAM cells to implement digital embedded non-volatile memory (eNVM) synaptic core allows write/read energy and latency improvements of about 53%/61% and 66%/17%, respectively, as compared to the SMTJ-based equivalent design. This is achieved by ensuring a reduced area footprint and a learning accuracy of about 91%. Such results make the DMTJ-based STT-MRAM cell a good eNVM option for neuro-inspired computing.

Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing With Adjacent Cells

In this brief, we present a novel low area joint 2T spin orbit torque magnetic random access memory (SOT-MRAM) cell architecture. The proposed joint 2T cell achieves up to 15 % of SOT-MRAM cell area reduction by sharing the diffusion regions of transistors between adjacent cells. In addition, the small bit-line capacitance of the proposed SOT-MRAM can lead to 27% read energy reduction in comparison to the conventional SOT-MRAM. When the proposed 1 MB SOT-MRAM is used as L2 cache of X86 processor, the gem5 simulation results show the average of 18% dynamic energy savings in various workloads of SPEC2006 benchmarks.

SOT and STT-Based 4-Bit MRAM Cell for High-Density Memory Applications

This article presents a multilevel design for spin-orbit torque (SOT)-assisted spin-transfer torque (STT)-based 4-bit magnetic random access memory (MRAM). Multilevel cell (MLC) design is an effective solution to increase the storage capacity of MRAM. The conventional SOT-MRAMs enable an energy-efficient, fast, and reliable write operation. However, unlike STT-MRAM, these cells take more area and require two access transistors per cell. This poses significant challenges in the use of SOT-MRAMs for high-density memory applications. To address these issues, we propose an MLC that can store 4 bits and requires only three access transistors. The effective area per bit of the proposed cell is nearly 58% lower than that of the conventional 1-bit SOT-MRAM cell. The combined effect of SOT and STT has been incorporated to design SOT-STT-based MLC that enables more energy-efficient and faster write operation than the regular MLCs. The results show that SOT-STT-based 4-bit MLC is 52.9% and 40% more efficient in terms of latency and energy consumption, respectively, when compared to 3-bit SOT-/STT-based MLC.

SOT and STT Based Four-Bit Parallel MRAM Cell for High-Density Applications

Spintronics based magnetic random-access memory (MRAM) offers nonvolatility, good scalability, high access speed, and low-power benefits over conventional complementary metal-oxide-semiconductor (CMOS) based memories such as dynamic random-access memory (DRAM) and static random-access memory (SRAM). Various structures including spin-transfer torque (STT), spin-orbit torque (SOT), and differential spin hall effect (DSHE) have been explored to improve scalability, power consumption, and access speed of the MRAM devices. Multilevel cells (MLCs) have been constructed using these structures to boost the storage capacity of the MRAM. This work proposes parallel DSHE (p-DSHE) and parallel SOT and STT based MRAM cell designs that can store 4-bits per cell, therefore, named as a four-level cell (FLC). p-DSHE based FLC uses pure SOT phenomena to write the MRAM cell while parallel SOT and STT based FLC utilizes both STT and SOT schemes. Both the designs are 62% area-efficient in comparison to SOT based 1-bit MRAM. Moreover, compared to STT based 3-bit MLC, p-DSHE based FLC is 97% and 59% more efficient in terms of energy and latency, while SOT and STT based FLC shows 63% and 39% reduction in energy and latency, respectively. Owing to these advantages, the proposed FLC designs can prove promising candidates for high-density memory applications.

Ultrathin perpendicular free layers for lowering the switching current in STT-MRAM

The critical current density Jc0 required for switching the magnetization of the free layer (FL) in a spin-transfer torque magnetic random access memory (MRAM) cell is proportional to the product of the damping parameter, saturation magnetization, and thickness of the free layer, αMStF. Conventional FLs have the structure CoFeB/nonmagnetic spacer/CoFeB. By reducing the spacer thickness, W in our case, and also splitting the single W layer into two layers of a sub-monolayer thickness, we have reduced tF while minimizing α and maximizing MS, ultimately leading to lower Jc0 while maintaining high thermal stability. Bottom-pinned MRAM cells with a device diameter in the range of 55–130 nm were fabricated, and Jc0 is the lowest for the thinnest (1.2 nm) FLs, down to 4MA/cm2 for 65 nm devices, ∼30% lower than 1.7 nm FLs. The thermal stability factor Δdw, as high as 150 for the smallest device size, was determined using a domain wall reversal model from field-switching probability measurements. With high Δdw and the lowest Jc0, the thinnest FLs have the highest spin-transfer torque efficiency.

Magnetic Nonvolatile SRAM Based on Voltage-Gated Spin-Orbit-Torque Magnetic Tunnel Junctions

This article proposes two different magnetic nonvolatile-static random access memory (MNV-SRAM) cell circuits for low-power, high-speed, and high-reliable backup operation with a compact cell area. They employ perpendicular magnetic tunnel junctions (p-MTJs) as nonvolatile backup storage elements and explore the spin-orbit torque (SOT) with the assistance of the voltage-controlled magnetic anisotropy effect (VCMA), referred to voltage-gated SOT (VGSOT), to perform the backup operation. By using an antiferromagnetic (AFM) layer that provides both an exchange bias and the SOT, no external magnetic field is required, making it suitable for practical applications. In addition, owing to the aid of the VCMA effect, the critical SOT write current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOT</sub> ) for 1-ns backup operation can be reduced significantly, thus resulting in high speed, low power consumption, and high reliability. Moreover, such resulted I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOT</sub> allows to be driven by the cross-coupled inverters in the SRAM cell, instead of a dedicated write driver, thereby leading to low cell area overhead. By using a commercial CMOS 40-nm design kit and a physics-based VGSOT-MTJ model, we have demonstrated their functionalities and evaluated their performance. Compared with previous SOT-based MNV-SRAM cell circuits, the proposed MNV-SRAM cell circuits can achieve lower backup energy dissipation, smaller backup delay, lower backup error rate and less cell area overhead without the assistance of the external magnetic field.

Hybrid FFT algorithm for fast demagnetization field calculations on non-equidistant magnetic layers

In micromagnetic simulations, the demagnetization field is by far the computationally most expensive field component and often a limiting factor in large multilayer systems. We present an exact method to calculate the demagnetization field of magnetic layers with arbitrary thicknesses. In this approach, we combine the widely used fast-Fourier-transform based circular convolution method with an explicit computation of the interaction between layers using a generalized form of the Newell formulas. We implement the method both for central processors and graphics processors and find that significant speedups for irregular multilayer geometries can be achieved. Using this method we optimize the geometry of a magnetic random-access memory cell by varying a single specific layer thickness and simulate a hysteresis curve to determine the resulting switching field.

Origin of the Resistance-Area-Product Dependence of Spin-Transfer-Torque Switching in Perpendicular Magnetic Random-Access Memory Cells

We report on an experimental study of current-induced switching in perpendicular magnetic random-access memory (MRAM) cells with variable resistance-area products (RAs). Our results show that in addition to spin-transfer torque (STT), current-induced self-heating and voltage-controlled magnetic anisotropy also contribute to switching and can explain the RA dependencies of the switching-current density and STT efficiency. Our findings suggest that thermal optimization of perpendicular MRAM cells can result in significant reduction of switching currents.

Area Efficient High Through-put Dual Heavy Metal Multi-Level Cell SOT-MRAM

This paper proposes a novel multi-level cell spin-orbit torque magnetic random-access memory (MLC SOT-MRAM) cell structure and validates its functionality and performance through simulation. The proposed memory cell comprises two uniform magnetic tunnel junctions (MTJs) that can be programmed separately by the energy efficient SOT technology through two different heavy metal electrodes. This permit employing both single and dual port architectures. The uniform cross-sectional area of the in-series MTJs stack simplifies the fabrication process. In addition, the cell structure requires only four terminals to successfully read and write the two bits. This allows accessing the two bits with only three access transistors, which achieves 25% smaller 1-bit effective area compared to the conventional single level cell (SLC) SOT-MRAM that requires four transistors. Simulation results based on an approximated dynamic model shows it offers nearly similar write energy consumption compared to the conventional SOT-MRAM.

Dependency of Multi-Level-Cell Behavior on Thickness of Top MgO Tunneling Barrier in Double Pinned Structure Perpendicular Spin-Torque-Transfer Magnetic Random Access Memory

These days dynamic-random-access-memory (DRAM) fabrication to scale down under 10-nm is complex which leads to high cost [1]. On the other hand, perpendicular spin-transfer-torque magnetic random access memory (p-STT MRAM) cell has a possibility of high-density integration with feature size of 4F2. Therefore, p-STT MRAM is the most powerful candidate of new memory instead of DRAM. In hence, p-STT MRAM requires high tunneling magnetoresistance (TMR) ratio greater than 150%, enough thermal stability (Δ=KuV/kBT) above 75 for a ten-year retention-time, and low switching current (J C0 ~ 1 MA/cm2) must be achieved for low power consumption [2-4]. However, the thermal stability is hard to maintain when the cell size is scaled down to 10 nm because the small volume of free layer leads to the changes of direction of spin by thermal agitation [5]. In this study, we designed a p-MTJ spin-valve with a double pinned structure to realize two-bit operation to overcome a larger scaling limit. We calculated four resistance states using relationship between the two different TMR of each MTJs. In particular, if the TMR of MTJ1 is half of MTJ2 and ratio of parallel resistance(Rp2/Rp1) is 0.8-0.9, the difference of each resistance state is equal. (see Fig. 1(b)) The TMR is mainly dependent on thickness of MgO tunnel barrier; therefore, we fabricated the p-MTJ spin-valve with a different thickness of MgO tunnel barrier (0.90 nm-1.35 nm) of MTJ1. Finally, we confirmed that the R-H curves match the four resistance states of p-MTJ with double pinned structure with our predicted results, and interval of resistance state is uniform when the thickness of top and bottom MgO are 1.36 nm and 1.10 nm as shown in Fig. 1(c). This implies that the double pinned p-MTJ spin-valve may be suitable for terabit integration compared to that of the single-bit operating p-STT MRAM memory cells. In the end, we report dependency of MLC behavior on thickness of top MgO tunneling barrier in double pinned structure pSTT MRAM. In addition, we present the MLC behavior of pSTT-MRAM with double pinned structure and show the thickness of top MgO for uniform resistance state. Acknowledgements This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No.2017R1A2A1A05001285) and Brain Korea 21 PLUS Program in 2014.

Stability Diagrams of a Tunnel Nanoheterostructure in the Free-Electron Approximation

One of important characteristics of a magnetic tunneling junction (MTJ) nanoheterostructure that is used as magnetic random access memory (MRAM) cell and is switched by the spin transfer torque (STT) effect is its stability diagram, which determines the range of values of the external magnetic field and applied voltage under which a cell is in one of two stable states. To numerically construct such diagrams, one usually uses the solution of the Landau–Lifshitz dynamic equation in the single-domain approximation along with phenomenological constants that determine the values of spin torque in the material. In the present paper, the problem of spin-dependent electron transfer in an MTJ structure is considered, whose solution in the free-electron approximation allows one to calculate the values of spin torque for a given material in any magnetic configuration of the system and apply them to the integration of the Landau–Lifshitz equation. The method used allows one to more precisely reproduce the shape of the stability diagram and predict the critical values of the magnetic field and voltage necessary to switch an MTJ-based MRAM cell.

High-speed write error rate evaluation of a voltage-torque magnetic random access memory cell

We developed a system for evaluating the write error rate of a voltage-torque magnetic random access memory cell running at 500 kbps, which is two orders of magnitude faster than the conventional system. This performance enhancement was realized by making the following modifications. First, the bias-tee combining the read and write channels in the conventional system was replaced with a high-speed semiconductor analog switch. Second, a custom amplifier/comparator circuit was built to detect the magnetization state at high-speed. It was confirmed that there was no sign of any thermal influence up to 500 kbps.

Magnetization switching in nanoelements induced by the spin-transfer torque: Study by massively parallel micromagnetic simulations

In this paper we present a detailed numerical study of magnetization switching in shape-anisotropic thin-film nanoelements. These elements are at present of the major interest for the applied solid state magnetism as main components of a new generation of conventional and spin-transfer-torque (STT) magnetic random access memory (MRAM) cells. To conduct this study, we have developed a highly efficient method for massively parallel micromagnetic simulations of the magnetization reversal in small-size nanoelements, which allows to fully exploit the large performance gain available on the GPU architecture (usually achievable only for large systems). We apply our method to the spin-torque-induced magnetization switching in elliptical nanoelements in presence of thermal fluctuations. Being able to compute simultaneously the reversal of up to 1000 such elements, we obtain the dependence of (i) the average switching time and (ii) the distribution density of switching times for individual elements on the element size with a high statistical accuracy. Analysis of these dependencies provides important insights into the physics of magnetization reversal in such systems. Comparison with analogous simulations in the macrospin approximation allows to determine the validity limits of the macrospin model. Our methodology can be applied for the optimization of the MRAM design regarding the information life time and significantly improve the prediction accuracy of write and read error rates of conventional and STT-based MRAM cells.

Physicochemical origin of improvement of magnetic and transport properties of STT-MRAM cells using tungsten on FeCoB storage layer

We investigated and compared the structural and magnetic properties of MgO/FeCoB based out-of-plane magnetized tunnel junctions at the thin film level and the magneto-transport properties of the corresponding patterned spin transfer torque magnetic random access memory(STT-MRAM) cells comprising either Ta1 nm or W2/Ta1 nm cap layers for different annealing temperatures up to 455 °C. The W material in the cap was found to improve the structural stiffness of the perpendicular magnetic tunnel junctions (pMTJs) and most importantly prohibits Fe diffusion from the FeCoB storage layer to the cap layer, remarkably improving the thermal robustness and magneto-transport properties of the stacks and of the corresponding patterned memory cells. As a result, the interfacial anisotropy constant of the MgO/FeCoB interfaces is improved by 17%–29% compared to the Ta cap. The STT-MRAM cells fabricated from the pMTJ stacks with the W/Ta cap reveal a significant improvement of the tunneling magnetoresistance and thermal stability factor, which are 120% and 52 as compared to 70% and 35 for the stack with the Ta cap, respectively. This improvement is ascribed to the enhancement of MgO crystallinity upon higher temperature annealing (425 °C) and prohibition of Fe out-diffusion.

Ultra-Low Write Energy Composite Free Layer Spin–Orbit Torque MRAM

A highly efficient exchange-coupled free-layer spin–orbit torque (SOT) magnetic random access memory cell is proposed for ultra-high-density memory. By exploiting typically unrealized benefits of SOT—in particular, its compatibility with low-damping magnetic insulators and the energy efficiencies associated with exchange coupling of hard/soft composite structures—a write energy of 18 aJ/bit for 1 ns switching is achieved. Furthermore, high magnetocrystalline anisotropy materials such as L10-FePt or L10-FePd are employed not only to facilitate achievement of ultra-high-density memory but also to allow for reduction of heavy metal layer volume and a reduction in write energy not seen in previous CoFeB-based cells. This energy is within a factor 72 of the theoretical limit of $60~k_{B}T$ . It also represents a factor of >500 improvement relative to state-of-the-art DDR4 DRAM cells.

Pulse-Width and Temperature Effect on the Switching Behavior of an Etch-Stop-on-MgO-Barrier Spin-Orbit Torque MRAM Cell

In this letter, we present a novel step spin-orbit torque magnetic random access memory (SOT-MRAM) cell structure and its switching behavior. A special stop-on-MgO etch etches away the hard mask and the pinned layer while retaining the free layer (FL) and MgO as part of the cell. The extended Ta/CoFeB/MgO layer is proved to be more tolerant to the etching non-uniformity of the Ta nanowire and improve etching yield. Although etching stops on MgO, the FL underneath the thin MgO has been rendered non-magnetic by the etching process. Recessed Cu pads were added to the Ta nanowire, which substantially reduces the overall resistance of the Ta nanowire. The general switching behavior of the step SOT-MRAM cells, such as pulse-width and temperature dependence of the switching currents, resembles that of a spin-transfer torque MRAM cell.

Design of Double Pinned Perpendicular Magnetic-Tunnel-Junction Spin-Valve Exhibiting Multiple Resistance States

Perpendicular spin-transfer-torque magnetic random access memory (p-STT MRAM) cells consist of a perpendicular magnetic tunnel junction and a selective device has been researched intensively because of the possibility of overcoming the scaling limitations of the current dynamic random access memory (DRAM) below the 10-nm design rule [1]. p-STT-MRAM requires high tunneling magnetoresistance (TMR) ratio greater than 150%, sufficient thermal stability (Δ=KuV/kBT) above 75 for a ten-year retention-time, and low switching current (J C0 ~ 1 MA/cm2) must be achieved for low power consumption [2-3]. However, the thermal stability is hard to maintain when scaling down in 10-nm scale of the p-STT MRAM cells for terabit integration. It requires high interfacial anisotropy K i to maintain the thermal stability requirement for 10-year retention time [4]. In this study, we designed a p-MTJ spin-valve with a double pinned structure to realize two-bit operation to secure a larger scaling limit (see Fig. 1(a)). We investigated the dependency of the number of [Co/Pt]n multilayers on the coupling strength to the pinned layers in order to control the spin-electron direction of the pinned layers. The total number of [Co/Pt]n SyAF multilayers ferro-coupled to the bottom pinned layer was reduced from 9 to 3 layers to reduce the roughness of the MgO tunneling barrier to increase the TMR ratio. Also, the number of [Co/Pt]n of the top upper SyAF multilayers was modulated so that the coercive field (H c) required to switch the spin-electron direction of the top pinned layer increased from about 0.3 kOe to 1 kOe which is sufficient to ensure the memory margin for two-bit operation, as shown in Fig. 1(b). Then, we investigated the multiple resistance states with the R-H loop of the double pinned p-MTJ spin-valve, as shown in Fig. 1(c). It showed four different resistance states depending on the spin-electron direction of the free layers and pinned layers as shown in Fig. 1(d) with a maximum TMR ratio of 166%. This implies that the double pinned p-MTJ spin-valve may be suitable for terabit integration compared to that of the single-bit operating p-STT MRAM memory cells. Acknowledgements This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No.2017R1A2A1A05001285) and Brain Korea 21 PLUS Program in 2014.

Accurate calculation and shaping of the voltage pulse waveform applied to a voltage-controlled magnetic random access memory cell

This paper presents procedures for calculating and shaping the voltage pulse waveform applied to a voltage-controlled magnetic random access memory (VC-MRAM) cell, which are indispensable experimental steps for studying the dynamic toggle switching of the VC-MRAM cell driven by the application of a high-speed voltage pulse. The calculation of the voltage waveform starts from the detailed characterization of each part of the pulse propagation path using a vector network analyzer. The obtained S-parameters are used to calculate the frequency response of the entire path. Next, the output waveform of the signal source is captured using a high-speed sampling oscilloscope, which is Fourier transformed, multiplied with the frequency response of the pulse propagation path, and inverse Fourier transformed to calculate the time domain voltage waveform applied to the device under test. We also present a procedure to shape the voltage waveform as desired by taking the reverse calculation process. The calculated and observed waveforms showed close agreement in both the waveform calculation and shaping.