SOT and STT Based Four-Bit Parallel MRAM Cell for High-Density Applications

Abstract

Spintronics based magnetic random-access memory (MRAM) offers nonvolatility, good scalability, high access speed, and low-power benefits over conventional complementary metal-oxide-semiconductor (CMOS) based memories such as dynamic random-access memory (DRAM) and static random-access memory (SRAM). Various structures including spin-transfer torque (STT), spin-orbit torque (SOT), and differential spin hall effect (DSHE) have been explored to improve scalability, power consumption, and access speed of the MRAM devices. Multilevel cells (MLCs) have been constructed using these structures to boost the storage capacity of the MRAM. This work proposes parallel DSHE (p-DSHE) and parallel SOT and STT based MRAM cell designs that can store 4-bits per cell, therefore, named as a four-level cell (FLC). p-DSHE based FLC uses pure SOT phenomena to write the MRAM cell while parallel SOT and STT based FLC utilizes both STT and SOT schemes. Both the designs are 62% area-efficient in comparison to SOT based 1-bit MRAM. Moreover, compared to STT based 3-bit MLC, p-DSHE based FLC is 97% and 59% more efficient in terms of energy and latency, while SOT and STT based FLC shows 63% and 39% reduction in energy and latency, respectively. Owing to these advantages, the proposed FLC designs can prove promising candidates for high-density memory applications.