Macrocell Array Research Articles

Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros

We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology, which enables the same fast access time with a smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-µm CMOS process and a 0.24-µm MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64bits of data. The area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, a wide read margin on a test chip is accomplished and 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.

Josephson macrocell array

A modified variable-threshold logic (MVTL) gate for use in Josephson LSI circuits is considered. A 7.6 K-gate Josephison macrocell array whose functions can be changed by wiring changing has been developed. Automatic design problems, such as AC powering and small fan-outs, are solved by constructing the macrocell with a three-phase powering system and developing a magnetically coupled unit cell. The chip contains 21440 Josephson junctions on a 5 mm*5 mm die and is fabricated using 1.5 mu m all-niobium Josephson techniques. An average delay of 5.3 ps/gate in the macrocell and a total chip power consumption of 23 mW have been obtained. >

30-ps 7.5-GHz GaAs MESFET macrocell array

An ECL-compatible GaAs 250-gate macrocell array has been successfully designed and fabricated using a three-level series gate low-power source-coupled FET logic (LSCFL) and a newly developed 0.4- mu m-gate self-aligned MESFET process. The unloaded propagation delay time was 30 ps/gate at a 2.4-mW/gate power dissipation. The loaded delay time with fan-out=3 and a 2-mm line length was as fast as 74 ps. The flip-flop toggle frequency was 7.5 GHz. A 2*2 asynchronous transfer mode (ATM) switch circuit was constructed on the macrocell array, and a maximum operation frequency of 2 GHz was achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A low-permittivity interconnection using an SiBN interlayer

A low-permittivity two-level interconnection process is presented. The key features of this process are the use of a low dielectric constant SiBN interlayer and the adoption of planarization using a two-stage etch-back process. The SiBN film is characterized from the standpoint of its device applications. The two-level interconnection process flow is described in detail. The effect of the SiBN interlayer in reducing the second wiring capacitance is compared to that of a conventional silicon nitride interlayer. This is demonstrated by fabricating a 33-stage ECL ring oscillator and a 2.1 kG macrocell array LSI.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

43-ps 5.2-GHz macrocell array LSIs

A family of bipolar macrocell array LSIs has been developed which has a basic delay of 43 ps/CML and a toggle frequency of 5.2 GHz/flip-flop. This family uses a cascaded-differential and single-ended CML circuit and a highly advanced super self-aligned process technology (SST-1B) which uses a selectively ion-implanted collector technology based on SST-1A. Using the macrocell array LSIs, performances of 1.2 ns/1.2 W for a 6-bit multiplier, and 4.3 ns/3 W for a 16-bit multiplier have been achieved. >

A macro cell array automatic layout system and its placement algorithm

A Macro Cell Array Automatic Layout System is described briefly and then an efficient placement algorithm is proposed which takes even distribution of signal nets as a main goal, and adopts constructive placement and iterative improvement simultaneously. In placement procedures, the effect of placement upon routing is combined with all placement procedures from the beginning to the end. In addition, this algorithm has a function which makes channel wiring density even. It has greatly reduced the failure possibility for layouting upon congested local areas. In concluding, some experimental results and chip layouts for real circuits are given.

30 Megabyte/Second FASTBUS Disk System for Image Storage

A high bandwidth Fastbus based disk system for use with real-time streams of image data in formats such as 30 frames/second of 1024 by 1024 pixels/frame with 8 bits of data per pixel has been designed for applications such as the medical imaging system previously described [1,2,3]. The storage medium is implemented with four Fujitsu parallel transfer disk modules, while the Fastbus interface features two-tiered double buffers, heavy microcoding, and no-handshake Fastbus operation at 160 megabytes/second in a pipelined ECL macrocell array. The system design was supported by the National Heart, Blood, and Lung Institute of the National Institutes of Health, U. S. Department of Health and Human Services under Phase I SBIR grant l-R43-HL36022-01. A funding request for Phase II SBIR funding to support construction of a prototype unit is currently pending.

Design and application of a 2500-gate bipolar macrocell array

A very high-speed 2500-gate Si bipolar macrocell array has been developed using a novel macrocell design approach and a 1-/spl mu/m rule advanced super self-aligned process technology (SST-1A). Using this macrocell array, a 16-bit parallel multiplier is designed and fabricated. The sophisticated circuit design of the macrocell array approach permits this complex function, which is equivalent to having 3024 NOR gates, using only 70% of the total of 756 internal cells. Consequently, a fast multiplication time of 7.5 ns is achieved with a 2.07-W power dissipation. Excellent performance with an average gate delay of 120 ps and average power dissipation of 0.365 mW is demonstrated for an equivalent NOR gate.

Current Status of the FASTBUS Micro-VAX

The present hardware, firmware, and software design and status of the Fastbus Micro-VAX, a two board Fastbus module packaging of the DEC Micro-VAX II computing system, will be described. The hardware currently features an Intel 80186, equipped with 64 kB of ROM, 32 kB of RAM, and an 82586/82501 Ethernet port, as a front end I/O processor, plus a high bandwidth Fastbus interface implemented in semi-custom ECL 100K VLSI with the Motorola MCA2500ECL macrocell array. Standard 80186 firmware implements multiple Fastbus segment drivers and interrupt receivers software compatible with the UPI, a limited Fastbus interprocessor network, and emulations of the DEC DEQNA Ethernet interface and an MSCP disk interface. Software includes device drivers for the non-DEC devices, plus appropriate standard access subroutines for the Fastbus and network devices. This work is supported by the U. S. Department of Energy under SBIR Contract DE-AC01-83ER80078.

A 333 ps/800 MHz 7 K-gate bipolar macrocell array employing 4 level metallization

An ECL100K-compatible, bipolar, subnanosecond macrocell array has been developed. A new macrocell structure is proposed, using a 2-/spl mu/m design rule and four-level metallization SST-2 process. A basic macrocell consisting of 10 transistors and 12 resistors is formed by the stretched Pt-Si patterns for the electrodes of base and resistor. The basic circuit structure is a two-level series-gated ECL circuit with emitter-follower output. The high performance of the 333 ps/cell and an 800-MHz toggle frequency of a master-slave flip-flop were achieved using a 0.2-mA switching current. The gate count of the chip is equivalent to 6.8 to 8.3K gates.

Thermal Studies on Pin Grid Array Packages for High Density LSI and VLSI Logic Circuits

The highest speed silicon logic chips are currently made using the emitter coupled logic (ECL) bipolar technology which inherently dissipates more power than other logic families. Recent developments include a macrocell array (MCA 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> ) logic chip dissipating up to 12 W of power over 0.47 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and there are plans to develop a technology chip dissipating 10 W of power over an area of 1.03 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , both to be used in high performance applications. It is essential that the packages housing these chips, have good thermal and electrical characteristics to fully realize the potential of these chips. Extensive computer-based thermal modeling and experimental studies were performed to design a high thermal performance ceramic pin array package utilizing the cavity down approach. Single-layer alumina, muitilayer alumina, and muitilayer beryllia-alumina composite packages were studied. Both unidirectional and omnidirectional heatsinks were computer modeled, designed, and tested in a wind tunnel. Power transistor and MCA 2 logic chips were used to simulate the power levels. Both parametric and infrared microscopic methods were used to determine the junction temperatures. Finite difference modeling calculations were performed for various package configurations and compared with experimental results. The work has resulted in packages meeting the thermal requirements. A beryllia-alumina composite substrate package with an omnidirectional heatsink is chosen to house the 12 W power dissipating MCA 2 chip. It has a measured value of 3.3°C/W for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Theta</tex> <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ja</inf> in 750 linear feet per minute (3.8 m/s) air flow at sea level. An all alumina substrate pin array package with an omnidirectional heatsink is chosen as the technology package to house the 10 W power chip. It has a measured value of 5.1°C/W for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Theta</tex> <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ja</inf> in 1000 lfm (5.1 m/s) air flow at sea level.

A 2500 gate bipolar macrocell array with 250 ps gate delay

An oxide-isolated walled-emitter structure has been developed to obtain high performance and high packing density. Using this process, a macrocell array having 2500 equivalent gates has been fabricated. A gate delay of 250 ps with a 1 mA current switch has been achieved. Special circuitry and macros have been incorporated on the LSI to enhance diagnostic capability at both the chip and the system levels. A pin array package with /spl theta//SUB JA//spl les/4/spl deg/C/W has been developed for the LSI chip.