Machine-model Electrostatic Discharge Levels Research Articles

Investigation of Human-Body-Model and Machine-Model ESD Robustness on Stacked Low-Voltage Field-Oxide Devices for High-Voltage Applications

Electrostatic discharge (ESD) robustness of low-voltage (LV) field-oxide devices in stacked configuration for high-voltage (HV) applications was investigated in a 0.5- $\mu \text{m}$ HV silicon on insulator (SOI) process. Stacked LV field-oxide devices with different stacking numbers have been verified in a silicon chip to exhibit both a high ESD robustness and latch-up immunity for HV applications. The effect of turn-on resistance in the stacked ESD protection device on ESD current waveform under human body model (HBM) and machine model (MM) ESD tests was studied. The resistance of stacked device has a significant impact on the ESD peak current and damping waveform, especially in MM ESD test. The MM ESD level can be increased by the numbers of LV field-oxide devices in stacked configuration, but the HBM ESD level is still kept the same. The mechanism to cause such a result has been theoretically analyzed in detail in this paper.

Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology

A resistor-less power-rail electrostatic discharge (ESD) clamp circuit realized with only thin-gate-oxide devices and with a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By skillfully utilizing the gate leakage current to realize the equivalent resistor in the ESD-transient detection circuit, the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> -based ESD detection mechanism can be achieved without using an actual resistor to significantly reduce the layout area in I/O cells. From the measured results, the new proposed power-rail ESD clamp circuit with an SCR width of 45 μm can achieve 5-kV human-body-model and 400-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current of 1.43 nA at room temperature under the normal circuit operating condition with 1-V bias.

Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology

An ultralow-leakage power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide devices and with silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit, the proposed power-rail ESD clamp circuit can achieve an ultralow standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device by modifying the layout structure. From the measured results, the proposed power-rail ESD clamp circuit with an SCR width of 45 μm can achieve 7-kV human-body-model and 350-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current in the order of nanoamperes at room temperature under the normal circuit operating condition with 1-V bias.

New Design of 2 $\times$ VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology

A new 2 VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. This new design has a low standby leakage current by reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit. The proposed design with an SCR width of 50 can achieve a 6.5-kV human-body-model ESD level, a 300-V machine-model ESD level, and a low standby leakage current of only 103.7 nA at room temperature under the normal circuit operating condition with 1.8 V bias.

A 16-kV HBM RF ESD Protection Codesign for a 1-mW CMOS Direct Conversion Receiver Operating in the 2.4-GHz ISM Band

A decreasing-sized π -model electrostatic discharge (ESD) protection structure is presented and applied to protect against ESD stresses at the RF input pad of an ultra-low power CMOS front-end operating in the 2.4-GHz industrial-scientific-medical band. The proposed ESD protection structure is composed of a pair of ESD devices located near the RF pad, another pair close to the core circuit, and a high-quality integrated inductor connecting these two pairs. This structure can sustain a human body-model ESD level higher than 16 kV and a machine-model ESD level higher than 1 kV without degrading the RF performance of the front-end. A combined on-wafer transmission line pulse and RF test methodology for RF circuits is also presented confirming previous results. The front-end implements a zero-IF receiver. It has been implemented in a standard 2P6M 0.18-μm CMOS process. It exhibits a voltage gain of 24 dB and a single-sideband noise figure of 8.4 dB, which make it suitable for most of the 2.4-GHz wireless short-range communication transceivers. The power consumption is only 1.06 mW from a 1.2-V voltage supply.

Design of 2$\times$VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology

A low-leakage 2× VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit composed of the silicon-controlled rectifier (SCR) device and new ESD detection circuit, realized with only thin-oxide 1× VDD devices, has been proposed with consideration of gate leakage current. By reducing the voltage across the gate oxides of the devices in the ESD detection circuit, the whole power-rail ESD clamp circuit can achieve an ultralow standby leakage current. The new proposed circuit has successfully been verified in a 1-V 65-nm CMOS process, which can achieve 6.5-kV human-body-model and 350-V machine-model ESD levels under ESD stresses, but only consumes a standby leakage current of 0.15 μA at room temperature under normal circuit operating conditions with 1.8-V bias.

On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress

A new electrostatic discharge (ESD) protection structure of high-voltage p-type silicon-controlled rectifier (HVPSCR) that is embedded into a high-voltage p-channel MOS (HVPMOS) device is proposed to greatly improve the ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional n+ diffusion into the drain region of HVPMOS, the transmission-line-pulsing-measured secondary breakdown current of the output driver has been greatly improved to be greater than 6 A in a 0.5- mum high-voltage complementary MOS process. Such ESD-enhanced VFD driver IC, which can sustain human-body-model ESD stress of up to 8 kV, has been in mass production for automotive applications in cars without the latchup problem. Moreover, with device widths of 500, 600, and 800 mum, the machine-model ESD levels of the HVPSCR are as high as 1100,1300, and 1900 V, respectively.

ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology

Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-/spl mu/m CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7 /spl plusmn/ 1 dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 /spl plusmn/ 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and high ESD robustness of the DA can be successfully codesigned to meet the application specifications.

Using diode-stacked NMOS as high voltage tolerant ESD protection device for analog applications in deep submicron CMOS technologies

A new high voltage tolerant (HVT) electro-static discharge (ESD) design adopts one forward biased P+/N-well diode in series of one stacked NMOS, called the diode-stacked NMOS, is proposed to reduce the total capacitance and maintain the high ESD performance. The device has been implemented in 0.18 μm CMOS logic technologies and finds the measured human body model and machine-model ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.