Abstract
A new high voltage tolerant (HVT) electro-static discharge (ESD) design adopts one forward biased P+/N-well diode in series of one stacked NMOS, called the diode-stacked NMOS, is proposed to reduce the total capacitance and maintain the high ESD performance. The device has been implemented in 0.18 μm CMOS logic technologies and finds the measured human body model and machine-model ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.