Using diode-stacked NMOS as high voltage tolerant ESD protection device for analog applications in deep submicron CMOS technologies

Abstract

A new high voltage tolerant (HVT) electro-static discharge (ESD) design adopts one forward biased P+/N-well diode in series of one stacked NMOS, called the diode-stacked NMOS, is proposed to reduce the total capacitance and maintain the high ESD performance. The device has been implemented in 0.18 μm CMOS logic technologies and finds the measured human body model and machine-model ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.