Machine Cycle Research Articles

A cache-based multiprocessor with high efficiency

Shared-memory multiprocessors to support concurrent languages for general-purpose multitasked systems are analyzed. To solve the traditional performance problems caused by memory access latency and conflicts, extensive caching of instructions and data is performed in each processor mode. Caches are private to each processor, and coherence is maintained in hardware between the caches. To maintain a good efficiency, several contexts are resident in each processor. On a miss in the cache, a microswitch to another resident context is operated by changing the program counter and a pointer in the register memory. The instruction set of each processor is RISC-like, so that a microswitch should waste few machine cycles. The proposed system has high efficiency, even when the number of processors increases and when the coherence overhead and conflicts are high. Models are developed to evaluate throughput and efficiency.

A receiver circuit for Josephson computer chip-to-chip logic signal transmissions

A receiver circuit for the transmission of logic signals through package connectors in a Josephson computer is developed. It utilizes new circuit construction. This construction gives operation unaffected by the noise which is induced on the signal transmission paths by high-frequency and high-level ac power current at the connectors. The power current noise reduction ratio at a power frequency of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</tex> = 250 MHz, which corresponds to a 2-ns machine cycle, is experimentally confirmed to be 0.15.

The GF11 supercomputer

GF11 is a parallel computer currently under construction at the IBM Yorktown Research Center. The machine incorporates 576 floating- point processors arranged in a modified SIMD architecture. Each has space for 2 Mbytes of memory and is capable of 20 Mflops, giving the total machine a peak of 1.125 Gbytes of memory and 11.52 Gflops. The floating-point processors are interconnected by a dynamically reconfigurable non-blocking switching network. At each machine cycle any of 1024 pre-selected permutations of data can be realized among the processors. The main intended application of GF11 is a class of calculations arising from quantum chromodynamics.

Josephson cross-sectional model experiment

This paper describes the electrical design and evaluation of the Josephson cross-sectional model (CSM) experiment. The experiment served as a test vehicle to verify the operation at liquid-helium temperatures of Josephson circuits integrated in a package environment suitable for high-performance digital applications. The CSM consisted of four circuit chips assembled on two cards in a three-dimensional card-on-board package. The chips (package) were fabricated in a 2.5-μm (5-μm) minimum linewidth Pb-alloy technology. A hierarchy of solder and pluggable connectors was used to attach the parts together and to provide electrical interconnections between parts. A data path which simulated a jump control sequence and a cache access in each machine cycle was successfully operated with cycle times down to 3.7 ns. The CSM incorporated the key components of the logic, power, and package of a prototype Josephson signal processor and demonstrated the feasibility of making such a processor with a sub-4-ns cycle time.

SEU Vulnerability of the Zilog Z-80 and NSC-800 Microprocessors

A detailed analysis of the SEU vulnerability of the Zilog Z-80 microprocessor is presented based upon data obtained with heavy ions and protons. The analysis demonstrates a method for separating upsets of the general purpose registers from upsets of the internal latches. Furthermore, the analysis shows that the bulk of the upsets observed below a LET value of 4 Mev-cmsq/mg is associated with upset of these internal latches. To obtain the data which made this analysis possible, a novel test technique was developed which associates all upsets with the machine cycle during which they first appear on the device pins. Limited data for the NSC-800 are included.

A fast pipelined DFT processor and its programming consideration

A new discrete Fourier transform (DFT) processor with a pipelined structure has been developed. This processor is designed to optimise computation of the pair of operationsAx0 ±Bx1, which is mostly encountered in various fast DFT algorithms. For real-valued data and coefficients, the processor needs only two machine cycles to calculate the pair of operations. A straightforward multiple-stage transform algorithm has been proposed to implement real-valued prime-factor or radix-type transforms. About half of the computation can be saved by taking into account the fact that transform outputs are conjugate pairs for real inputs. The short Winograd Fourier transform algorithm is suggested as a basic building block for large transforms because it is more efficient than the fast Fourier transform.

Tevatron Extraction Microcomputer

Extraction in the Fermilab Tevatron is controlled by a multi-processor Multibus microcomputer system called QXR (Quad eXtraction Regulator). QXR monitors several analog beam signals and controls three sets of power supplies: the ''bucker'' and ''pulse'' magnets at a rate of 5760 Hz, and the ''QXR'' magnets at 720 Hz. QXR supports multiple slow spills (up to a total of 35 seconds) with multiple fast pulses intermixed. It linearizes the slow spill and bucks out the high frequency components. Fast extraction is done by outputting a variable pulse waveform. Closed loop learning techniques are used to improve performance from cycle to cycle for both slow and fast extraction. The system is connected to the Tevatron clock system so that it can track the machine cycle. QXR is also connected to the rest of the Fermilab control system, ACNET. Through ACNET, human operators and central computers can monitor and control extraction through communications with QXR. The controls hardware and software both employ some standard and some specialized components. This paper gives an overview of QXR as a control system; another paper summarizes performance.

A Hierarchical Standard Cell Approach for Custom VLSI Design

A custom VLSI design technique, using an integrated CAD system is described. The design system features on the hierarchical design process and layout design capability by system designers (customers). As for application, high-performance LSI's for 16-bit CPU were developed. The LSI design was accomplished in a short period (three months with three designers) due to the hierarchical standard cell approach. The LSI chip contains about 20 K transistors in an 8.84 mm X 8.88 mm die area. High-speed operation (machine cycle = 200 ns) and a high density of 291 transistors/mm2 were obtained with low power consumption (1.2 W) owing to the mixed-MOS type standard cell library and this approach.

One-Line Machine and Process Diagnostics

Good progress has been made in the development of diagnostic systems for machines. The computer has been used effectively to shorten the time and reduce the skills required by maintenance personnel for solving problems. Particular progress has been made in the areas of the relatively infrequent but complex CNC problems and the more frequent but less complex machine cycle hangups. There is strong research interest in the use of vibration signatures to anticipate the failure of mechanical elements such as slideway and spindle bearings. Commercial efforts in process sensing are not nearly as successful. New sensors are becoming available at a rapid rate. However most of them fall short of the desired goals. Research in this field is going on at many institutes and in many directions. It seems likely that no single breakthrough will solve all problems but that many successes will be found which will apply over limited areas.

Analysis of branch prediction strategies and branch target buffer design

CPU pipelines need a steady flow of instructions in order to function with maximum effectiveness. Branches which change the expected order of instruction execution require that the pipeline be reloaded, resulting in several lost machine cycles per such branch. By examining the type of branch and the past execution behavior of that branch (taken/not taken) it is possible to predict with high accuracy whether the branch will be taken or not taken, and by remembering the previous branch target (destination), to predict the current branch target. In this paper we use a systematic approach to selecting good prediction strategies. Our studies are based on 26 program address traces grouped into four IBM 370 workloads (scientific, commercial compiler, supervisor) and CDC 6400 and DEC PDP-11 workloads. Our results show the effectiveness of various prediction strategies, the number of past branches that should be remembered, the amount of state required for each and the effect of workload and branch type. Improvements of from 5% to 20% can be expected in CPU performance when a branch target buffer is installed. We also consider issues relating to the implementation of real branch target buffers.

An Injection Moulding Control Scheme for Selected Product Features

In spite of considerable efforts to optimize the parameters of the injection moulding machine, it failes to guarantee a constant product quality. The machine and raw-material parameters are influenced by disturbances, which impairs a constant part quality. The paper describes a cyclic measurement and control system for two selected product features, which is superimposed on the conventional machine control systems. The experimental modelling is used for the estimation of cyclic process models which simplifies the complicate process of weight and length formation during one machine cycle. The models relate the product features to the machine settings and due to its minimized structure it can be updated on-line. The paper includes the control scheme and the adaptive method for weight control. Simulation results of the closed weight control loop are presented. The industrial applicability of this quality control concept is discussed.

An Intelligent Digital Controller in the Formation Process of Glass Bottles

An automatic digital controller was developed for a glass forming machine with the purpose of maintaining bottle consistency by regulating the formation process cycle period. Regulation was achieved by using a microprocessor with instrumentation interfaces to external sensors and actuatores and the software logic for predicting estimates of machine cycle periods based on present and past measurements. The controller is capable of compensating up to 12% variational changes in the cycle periods without mechanical failure. Furthermote, the software contains safeguards which continue to predict estimates of machine cycle periods in the event that the reference signal is lost. Results from on-line production measurements indicate a consistency in the quality of bottles produced during times when the cycle signal is lost or is varying.

AC powered Josephson latch circuits

The design and experimental verification of a novel Josephson latch circuit are reported. This latch is powered by the same AC power as that used for the latching logic circuits, thus eliminating the additional power supply demanded by other Josephson latch circuits. A SET/RESET latch and a 2-port DATA latch with LSSD capability are reported. WRITE delays of 110 p.s. and 65 p.s., respectively, for the DATA and the SET/RESET modes of operation have been estimated using computer simulations. The data stored in the latch is read out into the SLAVE circuit before the AC power supply waveform completes its polarity transition; thus, the read operation does not contribute any delay to the machine cycle. Experimental latch circuits have been fabricated using a 2.5 /spl mu/m Pb-alloy process. The experimental results are discussed. The experimental latch has been operated at cycle times approaching 1 ns and the risetime of the current transfer in the latch storage loop is measured using on-chip sampling to be about 100 p.s., in good agreement with computer simulations.

A new register file structure for the high-speed microprocessor

The pipeline operations of the register file in a microprocessor are analyzed in detail. Conventional register files, two-port static RAMs, have two problems in successive write-to-read operations. (1) A read-time error takes place when the transition of the W/R mode and the transition of register address occur simultaneously. (2) A write-time error takes place when the supply voltage is slow. A new register file structure is proposed, which has three address word lines and four data bit lines for each memory cell. This structure enables the independent write and read operations to each other, and can solve the two problems. By using this register file structure, a new 16 bit microprocessor with 250 ns machine cycle time is successfully developed. Several other features of this processor are also explained and discussed.

Rectangular Transforms for Digital Convolution on the Research Signal Processor

The Rectangular Transform (RT) method for computing convolutions belongs to a family of Reduced Computational Complexity (RCC) algorithms. Convolution calculations by the RT method were programmed for the Research Signal Processor (RSP) and run on the RSP simulator, giving tabulations of numbers of RSP machine cycles. One of the original objectives was to see how well the original RSP architecture was suited to the RCC algorithms and to be able to make suggestions for possible changes. The results are also intended to demonstrate the efficiency of the RT convolution algorithms on a microprocessor with a limited instruction set and to show how to construct efficient RT programs for digital convolution. All results are given for the original RSP, as it was before the modification which resulted in the Real-time Signal Processor described in another paper in this issue.

Machine cycle simulator for a microprocessor

The technique used in the construction of a simulator for a processor affects the range of applications for which the simulator can be used. A machine cycle simulator has been constructed for the MC68000 microprocessor, and some of the advantages of this technique are discussed.

System Development and Technology Aspects of the IBM 3081 Processor Complex

The IBM 3081 Processor Complex consists of a 3081 Processor Unit and supporting units for processor control, power, and cooling. The Processor Unit, completely implemented in LSI technology, has a dyadic organization of two central processors, each with a 26-ns machine cycle time, and executes System/370 instructions at approximately twice the rate of the IBM 3033. This paper presents an overview of the advances in technology and in the design process, as well as enhancements in the system design that were associated with the development of the IBM 3081. Application of LSI technology to the design of the 3081 Processor Unit, which contains almost 800 000 logic circuits, required extensions to silicon device packaging, interconnection, and cooling technologies. A key achievement in the 3081 is the incorporation of the thermal conduction module (TCM), which contains as many as 45 000 logic circuits, provides a cooling capacity of up to 300 W, and allows the elimination of one complete level of packaging--the card level. Reliability and serviceability objectives required new approaches to error detection and fault isolation. Innovations in system packaging and organization, and extensive design verification by software and hardware models, led to the realization of the increased performance characteristics of the system.

A Josephson technology system level experiment

This letter describes the first system level test vehicle in Josephson technology. The experiment consists of four circuit chips assembled on two cards in a high density, 3-dimensional, card-on-board package. A data path, which is representative of a critical path of a future prototype processor, was successfully operated with a minimum cycle time of 3.7ns. The path simulates a jump control sequence and a cache access in each machine cycle. This experiment incorporates the essential components of the logic, power and package portions of a Josephson technology prototype.

Digital Signal Processor: Architecture and Performance

This paper describes the DSP, a recently developed integrated circuit implementing a programmable digital signal processor. The single-chip device is fabricated in depletion-load NMOS and is packaged in a 40-pin DIP. It has the speed, precision, and flexibility for a variety of telecommunication applications. The processor can decode an instruction, fetch data, perform a 16- by 20-bit multiplication and a full 36-bit product accumulation in one machine cycle of 800 ns. This permits the realization of signal processing functions of such applications as dual-tone multifrequency receivers or low-speed data modems with a single device. The arithmetic precision of the processor is also sufficient for many voice signal applications.

Optimization of Microprograms

This paper describes a microprogram optimization technique called MORIF. The technique is general enough to treat machines whose microoperations require multiple machine cycles on a subcycle basis. The technique is applicable to microinstruction formats varying from horizontal to partially encoded, and to vertical. The technique includes global optimization algorithms for microprograms containing loops and recursive subroutines. Evaluation of the technique is performed from both the viewpoints of the complexity of the devised algorithms, and efficiency of generated object microcodes.