LTPS TFT Research Articles

59.3: Bridged‐grain (BG) Eximer Laser Annealing (ELA) Polycrystalline Silicon Thin Film Transistors (TFTs)

AbstractA new technique bridged‐grain (BG) was introduced. Using this BG eximer laser annealing (ELA) poly‐Si as an active layer, the grain boundary effects can be reduced. Important electrical properties such as sub‐threshold swing, threshold voltage, maximum field effect mobility, leakage current, on‐off ratio and device uniformity across the substrate can all be improved using the present technique. The improvement can be achieved at low cost, thus making inexpensive, high performance LTPS TFT a reality.

59.4: Rapid Dehydrogenation Technology of a‐Si using Xe Flash‐Lamp Annealing

AbstractFeasibility of the flash lamp annealing (FLA) process is tested for rapid dehydrogenation of a‐Si:H films without any damage on the glass substrate. Pulse duration of the flash lamp is 100 μs and the annealing process was carried out at room temperature. As the pulse energy density increases, hydrogen content in a‐Si films decreases. Thin film transistors based on the FLA dehydrogenation process have mobility of 108 cm2/V‐s and sub‐threshold swing of 0.39 V/dec. 14″ qFHD AMOLED displays have been fabricated using FLA. It is expected that the FLA process can further reduce manufacturing cost of LTPS TFT backplanes for large area AMOLED displays, because the FLA process can be applied not only for the dehydrogenation process but also for the crystallization and dopant activation processes.

A New Low Temperature Polycrystalline Silicon Thin Film Transistor Pixel Circuit for Active Matrix Organic Light Emitting Diode

This study presents one novel compensation pixel design and driving method for active matrix organic light-emitting diode (AMOLED) displays that use low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with a voltage feed-back method and the simulation results are proposed and verified by SPICE simulator. The measurement and simulation of LTPS TFT characteristics demonstrate the good fitting result. The proposed circuit consists of four TFTs and two capacitors with an additional signal line. The error rates of OLED anode voltage variation are below 0.3% under the threshold voltage deviation of driving TFT (ΔVTH = ±0.33 V). The simulation results show that the pixel design can improve the display image non-uniformity by compensating the threshold voltage deviation of driving TFT and the degradation of OLED threshold voltage at the same time.

77.1: Invited Paper: TFT Technologies for Flexible Displays

AbstractThe technology issues on a‐Si:H, LTPS, oxide and organic TFTs on flexible substrates are discussed based on our experimental data. The performance of the a‐Si:H TFTs on flexible graphite is the same as that on glass, the LTPS TFT on metal foils exhibited a field‐effect mobility of > 100 cm2/Vs, the oxide TFT on PI showed the mobility of 13 cm2/Vs with high on/off current ratio and OTFT on PEN exhibited a field effect mobility of > 0.1 cm2/Vs. Therefore, the OTFT is suitable for the backplane of e‐paper display, LTPS TFT on metal foil and oxide TFT on PI appear to be suitable for flexible AMOLED.

Effect of bias stress on mechanically strained low temperature polycrystalline silicon thin film transistor on stainless steel substrate

This paper reported the variation in performance of bias stressed low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) fabricated on metal foil substrate for flexible display applications. The mobility, threshold voltage (Vth), and trap density (Nt) of the proposed p-channel poly-Si TFT as a function of curvature radii were investigated. The significant increase in Vth by 9% was observed as the compressive or tensile mechanical strain increases to 0.1%. In addition, the hole mobility increases by 7% due to an increased compressive strain of 0.1%, while hole mobility decreases by 3.5% with the increase in tensile strain of 0.1%. After dc bias stressing, the LTPS TFT with mechanical strain had better performance than that on flat state in both the mobility drop and Vth shift. Mechanical strain influences the lattice arrangement and electric field at the drain electrode region that resisted device degradation in early stressing period.

Fabrication of Novel Three-Step Drift-Doped Low-Temperature Polycrystalline Silicon Lateral Double-Diffusion Metal–Oxide–Semiconductor Using Excimer Laser Crystallization

Low-temperature polycrystalline silicon (poly-Si) thin-film transistor lateral double-diffusion metal–oxide–semiconductor field-effect transistors (LTPS TFT LDMOSFETs) and lateral insulated-gate bipolar transistors (LIGBTs) were fabricated by combining a thin-film transistor with a power structure, three-step drift doping, and excimer laser annealing. The maximum breakdown voltage of the three-step drift-doped LTPS-LDMOS after excimer laser annealing is 286 V with a 35 µm drift region length (Ldrift). The specific on-resistance is low (approximately 9 Ω cm2) and the ON/OFF current ratio is about 1.28 ×106 with Ldrift = 15 µm. The subthreshold swing (SS) is about 1 V/decade. Comparing the three-step drift-doped LDMOS with the three-step drift-doped LIGBT under the same processing conditions clearly indicates that the breakdown voltage and current capacity of LIGBT exceeds those of LDMOS.

Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications

Low-temperature polycrystalline-silicon thin-film transistor (LTPS TFT) has emerged as one of the promising candidates for low-power low-cost applications on flexible substrates. In this paper, we propose a statistical simulation methodology to estimate parametric variations in scaled LTPS TFT due to the inherent properties [such as the number, location, and orientation of grain boundaries (GBs)] of the polycrystalline material. Our simulation technique employs the response surface method (RSM) to consider multiple process parameters which affect the performance distribution of LTPS TFT devices/circuits. Simulation results show that inherent GB variations result in multimodal delay distributions in basic logic building blocks (inv, nand, and nor) in scaled LTPS TFT technology, contrary to unimodal distributions in conventional bulk CMOS technology. We also observed that with increasing logic depth, the multimodal distribution converges to a unimodal distribution. Hence, to ensure robust and stable functionality of TFT technology under inherent process variations, we propose a multifinger (MF) design technique to improve the reliability of TFT circuits and to reduce the impact of GB-induced variations on TFT performance. Simulation results obtained from a 20-stage inverter chain show that by applying the proposed MF-based design, one can achieve 28% and 61% reductions in delay variations using two- and four-finger structures, respectively.

The Electrical Properties of Low Temperature Polycrystalline Si Thin Film Transistor Prepared by Nickel-ALD Process

We have fabricated low temperature polycrystalline Si thin film transistors (LTPS TFTs) for flat panel displays. In this work, metal induced crystallization (MIC) using atomic layer deposition (ALD) was employed to obtain poly-Si as an active layer in LTPS TFTs. The small amounts of nickel atoms by ALD were deposited on amorphous Si to minimize the metal contaminations. The poly-Si thin films have large and uniform grains with average size of 27 um by self-limited reaction process of ALD. The n-type LTPS TFT exhibits a high field effect mobility of about 76 cm^2/Vs, a sub-threshold slope of 0.09 V, a threshold voltage of 4.79 V, and an on-off ratio of 4.9 x 10^6

38.4L: Late‐News Paper: A New Low‐Power Driving Method for High‐Resolution Mobile IPS Panels

AbstractHigh‐resolution displays are now needed for mobile equipment, not only for cell phones, but also for other devices such as ultramobile PCs and mobile Internet Protocol Television s (IPTV). We have developed a new low‐cost and low‐power driving method for the high‐resolution IPS panel on the LTPS TFT platform. This method drives common electrodes separated by each line. So it can reduce inversion frequency, compared with “dot‐inversion” or “line‐inversion”. We also developed a prototype of a 5‐inch WXGA (1366 × 768) using our new driving method and confirmed good display quality and a low‐power consumption that was nearly equal to that of frame inversion.

Design of LTPS TFT Current Mode Multiplexer and MUX‐based Logic Gates

With the aim of creating a high‐quality display system with value‐added functions, we designed a current mode multiplexer for LTPS TFT devices. The multiplexers had less than 1 volt logic swing, and speed improvement was evident compared with that of conventional CMOS architecture. We refined the multiplexer to achieve a more stable current steering operation. By using the versatility of the multiplexer, a new NAND/AND and NOR/OR logic gates were designed through the simple modification of signal connections. Two micron LTPS TFT parameters were used during the HSPICE simulation of the circuits.

Poly-Si Thin-Film Transistors: An Efficient and Low-Cost Option for Digital Operation

In this paper, we propose an optimization methodology to design low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) for submicrometer ultralow-power digital operation. LTPS TFTs incur low fabrication cost and can be fabricated on a variety of substrates (flexible such as polymer, glass, etc.). LTPS TFT has significantly reduced mobility, resulting in reduced driving current; however, we show that, for ultralow-power subthreshold operation (Vdd < Vth) , LTPS TFTs can be optimized to achieve comparable performance as a single-crystalline silicon (c-Si) silicon-on-insulator (SOI). For LTPS TFTs with TS1 < 10 nm , ring oscillators (operating in subthreshold region) show significant reduction in intrinsic delay when the midgap trap density gets properly controlled (< 1012 cm-2) after hydrogenation with less dynamic energy consumption under isostatic power consumption compared to a c-Si SOI MOSFET. We also address the inherent variations in grain boundaries at device and circuit levels to gain practical insights.

Systematic design method for low power, high speed LTPS TFT based CML inverter/buffer

Progress in LTPS TFT technology enabled the system-on-panel to prevail in small FPDs. And high speed TFT circuit technique is essential for expanding the system-on-panel applications. In this work, all p-channel, LTPS TFT, current mode inverter/buffer is introduced. To overcome the power hungry nature of the current mode circuit, small logic swing, complementary input, and systematic design method have been developed. The design method is essential tool to obtain the best trade off between power and delay. It is proved that the CML inverter/buffer can be designed to consume less power and to operate at higher speed than CMOS inverter.

Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in LTPS TFTs. That is, when performing the NBTI measurement, the LTPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the LTPS TFT circuitry design.

MONOS memory in sequential laterally solidified low-temperature poly-Si TFTs

A metal-oxide-nitride-oxide-polysilicon (MONOS) memory device fabricated by sequential lateral solidified (SLS) low-temperature polycrystalline silicon (poly-Si) technology on a glass substrate was investigated. The Si protrusions at grain boundaries (GBs) as a result of the SLS process can be well controlled and located along the width direction of the transistor. Protrusions at the GBs are utilized as emitting source to achieve a MONOS memory device with low operation voltage (/spl les/ 20 V), fast program/erase time, and wide V/sub th/ window by field-enhanced channel hot electron injection for programming and field-enhanced band-to-band tunneling-induced hot hole injection for erase. This is the first study to demonstrate a nonvolatile memory device in low-temperature poly-Si thin-film transistor (LTPS TFT) technology, which can be integrated with TFT-liquid crystal display, to reduce power consumption for mobile applications.

Incorporation of input function into displays using LTPS TFT technology

Abstract— A new display in which an input function is incorporated has been developed by using LTPS TFT technology. A new circuit configuration that includes a lateral p‐i‐n diode with an in‐pixel amplifier, an LTPS A/D converter on the periphery of the glass substrate and an external image‐processing LSI is presented. The experimental results of two major applications of the image‐capture function and touch‐panel function are discussed.

64.2: Full Color 100 dpi AMOLED Displays on Flexible Stainless Steel Substrates

We demonstrate full color, top emission, active matrix OLED displays on flexible stainless steel substrates. The 100 dpi QVGA displays are driven by LTPS TFT backplane with excimer laser annealed poly-Si. To our knowledge this is the world's highest resolution full color flexible AMOLED display on steel foil demonstrated to date. Encapsulation is by a multilayer thin film.

High performance LTPS TFT with very large grains produced by sequential lateral crystallization

We report the structural and electrical properties of polycrystalline silicon on glass crystallized by using a CW Nd:YVO 4 laser. Various niicrostmctures appear on amorphous silicon after a scanning of the laser regardless of - crystallization process parameters such as laser power and scan speed. The crystallized region could be characterized by their grain size as 3 distinct regions; RTA-SPC (rapid thermal annealed-sotid phase crystallization) region, small-grain region and SLC (sequential lateral crystallization) region with very large grains of ∼10 μm. To verify its electrical properties, p-ch TFTs were fabricated on the 3 different regions. The characteristics of TFTs on SLC region were superior to those on other regions and average performances of SLC poly-Si TFTs were u fe = 132 cm 2 /Vs, V th = -4.6 V, S.S. = 0.5 V/dec, and I off = ∼1 dA/μm at V d = -10 V. respectively.

27.2: Characterizations of Flash Memory on Glass Using LTPS TFT with an Ultra-Low-Roughness Poly-Si∕SiO[sub 2] Interface

In this paper, flash memories using low temperature poly-Si thin- film transistors (LTPS-TFTs) with oxide-nitride-oxide (ONO) stack structure on glass was studied and fabricated. The surface roughness Rms of poly-Si implemented in this work is less than 20A. For 10 ms program/erase (P/E) pulse time, the threshold voltage window of memory is 1.5V and it maintains a wide threshold voltage window after 104 P/E cycles.

Design and analysis of current mode low temperature polysilicon TFT inverter/buffer

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

44.2: New Driving Method with Current Subtraction Pixel Circuit for AM-OLED Displays

A new current programmed driving method with current subtraction pixel circuit has been developed for LTPS AM-OLED displays. The new driving method enables to program low brightness signal current for larger sized panel and compensate electrical characteristic variations of LTPS TFT. Consequently, we can achieve high contrast ratio and good pixel-to-pixel luminance uniformity for LTPS AM-OLED displays.