LSI Circuits Research Articles

New phase-mode logic gates with large operating regions of circuit parameters

We propose new phase-mode logic gates with large operating regions of circuit perimeters. In the phase-mode logic, logic circuits are realized by combination of ICF (INHIBIT controlled by fluxon) gates. The function of the ICF gate can be achieved by the two gates which are an INHIBIT gate and an AND gate. These two gates are fabricated by NEC 2.5 kA/cm/sup 2/ Nb/AlOx/Nb standard process and successfully demonstrated. A Monte-Carlo calculation is used for evaluating yields of the gates. From 1000 calculations for each gates, we show that each yield of the INHIBIT gate and the AND gate does not decrease with increasing /spl sigma/=7% and /spl sigma/=9% which are the standard deviations of the parameter spreads. A realization of high-reliability LSI circuits will be expected by using these gates.

Quantum Gates by Coupled Quantum Dots and Measurement Procedure in Field-effect-transistor Structure

Coupled quantum-dot system in semiconductor is considered to be one of the promising candidates of quantum computer. It will be most desirable that the quantum computing devices are implemented into the same substrate as the widely used LSI circuits. From this viewpoint, the quantum computer of coupled quantum dots of semiconductors is presented concentrating on the controlled-NOT-gate operation. The decoherence time of the quantum computation and the measurement procedure by field-effect-transistor structure are discussed.

Study of LSI circuit for learning and odor recognition using 1bit data stream signal processing method

Study of LSI circuit for learning and odor recognition using 1bit data stream signal processing method

TOWARDS A NEARLY - MINIMAL TEST FOR MICROPROGRAMMABLE-MICROPROCESSORS A BIT - SLICED CASE STUDY

Conventional testing methods of digital systems are not practical for microprocessors due to: - Their high density of integration ( VLSI) , lack of information about their internal physical structure , internal test points are not accessible , impossibility of inserting new test points in an integrating chip with a limited number of external leads (pins ) and due to the nonprecision of hardware failure modes of new technologies such as CMOS,bipolar, etc. - Moreover, the conventional test methods have two serious limitations concerning their application for the verification of LSI circuits: - They consider the SSI components (gates, flip-flops, ....) as the primitive test elements. - They apply fault models based primarily on the s-a-O & s-a-1 model which associates faults to the connections between those basic elements. Bit-sliced microprocessors represent an important class of LSI components (microprogrammable ). A microprogrammed system can be generally tested by a suitable microprogram added to its normal operation microprograms This paper presents a methodology for generating a test microprogram for one of the recent powerful bit-sliced microprocessors (the superslice Am 2903).The test procedure is based on a fault model that takes into account a large variety of faults encountered with such microprocessors . The fault model is formulated at: a higher level in terms of functional modules such as the ALU, memory and multiplexers. The derived test is nearly — minimal and its execution does not speed down the system operation

Scalable 10 Gbit/s 4 × 2 0.25 µm CMOS/SIMOXATM switch LSI circuitbased on distributed contention control

A scalable 10 Gbit/s 4 × 2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput, 0.25 µm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.

Novel integrated photodetector on Si LSI circuits. Optically controlled MOSFET

We have demonstrated a novel integrated photo-detector on Si large-scale integration circuits. This device integrated the light absorption region on the gate of metal-oxide-semiconductor field-effect transistor (MOSFET), and the long wavelength light controls the current of MOSFET. The GaInAs-InP multiple-quantum-well absorption region and SiO/sub 2/ of the MOSFET were directly bonded. From the experimental results, we confirmed that the light-controlled current was increased by shortening the gate length of the MOSFET, and that an 1850 A/W responsivity was obtained in a 3.5-/spl mu/m gate length device using an irradiation of 1.5-/spl mu/m wavelength light.

High on-off ratio and responsivity in integrated optically controlled HEMT

High on-off ratio and high responsivity was obtained in a novel integrated optically controlled HEMT. The integrated structure of the device was composed of a p-i-n photodiode region and a HEMT region. These two regions were bonded using direct wafer bonding technique. When a laser light with a wavelength of 1.55 /spl mu/m was irradiated on the absorption region, on-off ratio of 12 dB and a responsivity of more than 300 A/W was obtained. This device is very attractive as the high efficiency optoelectronic (OE) transformer directly integrated on the LSI circuits.

Fabrication of submicron Nb/AlO/sub x//Nb Josephson junctions using ECR plasma etching technique

It is important to develop a high-yielding and reproducible fabrication process of submicron Nb/AlO/sub x//Nb Josephson junctions to improve the integration level and the operating speed of Josephson LSI circuits. For this purpose, we have developed a junction fabrication process by introducing an electron cyclotron resonance (ECR) plasma etching technique with CF/sub 4/ gas. In the ECR plasma etching technique, highly anisotropic etching of Nb was achieved. Over-etching was reduced by 86%. We have successfully fabricated Nb/AlO/sub x//Nb junctions with critical current density of 10/sup 4/ A/cm/sup 2/ using the cross-line patterning (CLIP) method and the electron beam (EB) lithography technique, where the size of the junctions was varied from 2 /spl mu/m to 0.5 /spl mu/m at 0.1 /spl mu/m intervals. High-quality submicron junctions for integrated circuits with small spread of critical current Ic was obtained. High uniformity of Ic was achieved. The characteristics of the fabricated junctions are discussed and compared with the junctions fabricated by RIE technique.

Error repair and knowledge acquisition via case-based reasoning

To cope with the knowledge acquisition bottleneck, the authors propose a new architecture combining rule-based reasoning (RBR), case-based reasoning (CBR) and knowledge acquisition technology in a system which solves pattern search problems. The RBR part searches for specified patterns in a large space represented by a network structure such as an LSI circuit diagram, which contains a great number of patterns and variations. It then carries out specified actions, such as fault diagnosis, on the patterns that are found. The outputs of the RBR part are transferred to the CBR part. The user of the system detects and repairs a few pattern detection errors caused by the RBR part. The CBR part detects and repairs all remaining errors which can be estimated from the user detected ones. The repaired results are sent back to the RBR part to recover the RBR output. The repaired results are also stored automatically in the case base. Similar cases are grouped in a same case family. The knowledge acquisition part relates each case family to an incomplete rule in the RBR knowledge base and proposes modifying the rule. Eventually, the system can obtain refined rules with the cooperation of domain experts. Thus, the problem solving process and knowledge acquisition process are performed cyclically. The architecture was successfully applied to a pair condition extraction problem for an analog LSI circuit layout system.

Design and evaluation of a novel enhancement mode FET logic gate configuration in AlGaAs/GaAs/AlGaAs quantum well HEMT technology

Evaluation of a high-performance logic gate configuration, utilising enhancement mode field effect transistors, is presented in AlGaAs/GaAs/AlGaAs quantum well HEMT technology. The performance of the gate in terms of speed, based on frequency divider measurements, shows a very high-speed operation achieved by utilising the bootstrap effect in the operation of the logic gate. The gate is suitable for the implementation of ultra-high-speed LSI circuits where high speed and noise margin are of critical importance.

WAVELETS IN HIGH-RESOLUTION RADAR IMAGING AND CLINICAL MAGNETIC RESONANCE TOMOGRAPHY

Coherent wavelets form a unified basis of the multichannel perfect reconstruction analysis-synthesis filter bank of high-resolution synthetic aperture radar SAR imaging and clinical magnetic resonance imaging MRI . The unitary filter bank construction is performed by the Kepplerian temporospatial Hilbert bundle strategy of physical astronomy, which allows stroboscopic and synchronous cross-sectional quadrature filtering of phase histories in contiguous local frequency encoding subband multichannels with respect to the rotating coordinate frame of quadrature reference. The Kepplerian temporospatial quadrature strategy and the associated unitary filter bank construction take place in symplectic affine planes and are implemented in the quadrature format of a phase-splitting network by Fourier analysis of the Heisenberg nilpotent Lie group G. The tomographic slices, frequency selected by the MRI scanner, are identified with the nontrivial coadjoint orbits of G. Thus the pathway of this paper leads from Keppler to Heisenberg and to the fascinating aspects of electronic engineering concerned with the implementation of the symmetries inherent to the semiclassical approach to clinical magnetic resonance tomography by large-scale integrated LSI circuit technology.

FUZZY BI- AND MULTI-PARTITIONING FOR CIRCUITS REPRESENTED BY HYPERGRAPHS

A new strategy for partitioning hypergraphs in complex LSI and VLSI circuits is presented. A new fuzzy net-cut model has been developed to treat multi-pin-nets without splitting into two-pin-nets. The combinatorial optimization algorithm is derived from statistical physics. The circuit graph is modeled as a highly coupled spin system and the mean field approximation is used to achieve linear time complexity. Fuzzy partitioning enables a qualitative and macroscopic approach by interpreting the mean values of the spin system as fuzzy membership degrees. The proposed strategy is tested with MCNC benchmark problems and compared to results achieved recently. The performance of the new algorithm is comparable with neural networks and simulated annealing, but much faster, because of its linear time complexity. Furthermore, the partitioning algorithm has been implemented in an industrial CAD design tool and results are given.

A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The ADU provides a cell-based interface between systems operating at different data rates (the high-speed interface being 2.5 Gb/s and the low-speed interface being 155/622 Mb/s), or can be used for building local high-speed switches and LANs. Self-timed first-in-first-out (FIFO) buffers are used for handling the speed gaps between domains operating at different clock rates, and a self-timed at receiver's input (STARI) interface is used at all high-speed chip-to-chip links to eliminate timing skews. A printed circuit board (PCB) with two ADUs in a distributed multiplexing-demultiplexing architecture has been developed, and the AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W in a standard 0.8 /spl mu/m E/D MESFET process.

Simple Method of Correcting Optical Proximity Effect for 0.35 µm Logic LSI Circuits

We propose a practical optical proximity correction (OPC) system, whose characteristics are simple and effective, for logic LSI circuits and outline all the steps for OPC. We also report the improvement of gate length deviations in a logic device with OPC.

An improved etching process used for the fabrication of submicron Nb/AlO/sub x//Nb Josephson junctions

It is important to develop a reliable and reproducible fabrication process of submicron Nb/AlO/sub x//Nb Josephson junctions to improve the integration level and the operating speed of the Josephson LSI circuit. For this purpose, we have developed an improved etching process by introducing a dummy etching process and using a scanning electron microscope (SEM) as an etching end-point detector. The dummy etching process improves the anisotropy of a reactive ion etching (RIE) process using CF/sub 4/. The etching residue around a junction is detected easily and correctly by the SEM observation. We have successfully fabricated Nb/AlO/sub x//Nb Josephson junctions with critical current density of 10/sup 4/ A/cm/sup 2/ using the cross-line patterning (CLIP) method and electron beam lithography, where the junction size was varied from 2 /spl mu/m to 0.5 /spl mu/m at 0.1 /spl mu/m intervals. High-quality submicron junctions for integrated circuits with suitable critical current variations were obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Evaluation and detection of CMOS-LSI with abnormal IDDQ

With the increase of LSI circuit complexity, an Iddq (Quiescent Vdd Supply Current) failure mode which is dependent on functional test patterns conspicuously appears even during the testing of the electronic circuits in a normal state. Over fifty failed samples are analyzed by using liquid crystal technique in order to establish the relationship between the failure modes and circuit operation. Two characteristics results of this investigation are indicated. First one is that a LSI circuit with an abnormal Iddq value involves physical damages in the LSI structure, such as unformed contacts, shorted lines, open lines and broken layout. The second one is that the cause of the appearance of normal operation is due to multiple functions within an elementary circuit block. The output value of a circuit block may not show the effect of penetration current from Vdd to ground giving the appearance of correct operation. Furthermore, the abnormal Iddq sample does not degrade under acceleration testing. An advanced method for the detection of abnormal Iddq values, which satisfies the mass production requirement of short test time with nearly the same effect as checking all test patters, is described.

A practical algorithm for DC operating‐point analysis of large‐scale circuits

AbstractSPICE‐type general‐purpose circuit simulators are used widely as a support tool for circuit design. It often happens, however, that the do operating‐point analysis does not converge. To cope with such a situation, various approaches have been proposed based on continuation methods with the global convergence property, but these have yet to come to the stage of practical application to large‐scale circuits.This paper proposes a practical algorithm which can be implemented on the general‐purpose circuit simulators with modified nodal formulation, for determining the de operating‐point of large‐scale circuits. As the first step, the concept of “modified cut‐set analysis” is introduced and some properties of the modified nodal equation are presented. Then it is shown, in practical circuits, that the convergence of the algorithm is theoretically guaranteed. The proposed algorithm is then implemented on an existing general‐purpose circuit simulator and applied to a bipolar analog LSI to demonstrate its effectiveness. For the LSI circuit formulated in 18, 553 modified nodal equations, the de operating point was determined in 270 minutes using an IBM RS6000‐550.

Chip layout design of a Josephson LSI circuit for examining high-speed operability by using a standard cell automatic placement and routing technique

A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hardware realization of a 2D IIR semisystolic filter with application to real-time homomorphic filtering

Hardware design and implementation of a 2D sample-and-hold semisystolic filter structure are presented. Log and antilog circuits are used with a high-frequency-emphasis IIR filter to provide homomorphic filtering. SPICE simulation using functional blocks as well as particulars on the hardware design with reference to specific device types and characteristics are discussed. A hardware prototype circuit using MSI and LSI circuits on a custom-made PCB is shown along with applications to real-time filtering of broadcasted TV images. >

A model for coplanar waveguide transmission line structures on semiconductor substrates

An accurate model for coplanar waveguide transmission line structures on semiconductive substrates is presented. The model is useful for simulating long (> 0.5 mm) interconnects on LSI and VLSI GaAs circuits as well as high speed Si ICs. When simulated in the frequency domain, the model shows an excellent match to measured S parameters of coplanar waveguide samples.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>