LSI Chip Research Articles

Microjoining of LSI Chips on Poly(ethylene naphthalate) Using Compliant Bump

We show that microjoining of LSI chips on a film made of poly(ethylene naphthalate) (PEN), whose glass transition temperature is 155 °C, can be realized by using a cone-shaped compliant bump for flexible electronics. A 20-µm-pitch area array of cone-shaped Au bumps was fabricated on a Si wafer by photolithography and electroplating. The counter electrode on the PEN film was composed of a Au (top)/Ni/Al (bottom) layered structure, where Ni and Au layers were deposited by electroless plating on patterned Al. The bonding was carried out at 150 °C. More than 10,000 connections with 108 mΩ/bump were achieved. Mechanical analysis using finite element method indicates that the joining is due to deformation of the cone-shaped Au bumps.

Embedded Active Packaging Technology for High-Pin-Count LSI With Cu Plate

We have developed a thin, reliable, low-thermal-resistance LSI packaging technology by embedding a high-pin-count LSI chip into thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 μm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for cooling, which is much thinner than the conventional flip chip ball grid array (FCBGA) package with a heat sink. Our package shows excellent warpage characteristics of only 34 μm at room temperature for 27 × 27 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in size. It is also possible to reduce the total package thickness to 0.46 mm by etching the Cu plate to half thickness, with keeping the warpage increase up to 117 μm. Low thermal resistance of 10.8°C/W is achieved for the packages with 0.5-mm-thick Cu plate at a wind velocity of 0 m/s, which is almost comparable to that of an FCBGA with a large heat sink. We have successfully demonstrated the functions of our packages using an LSI tester and personal-computer-like system board. They have also passed a 1000-cycle package-level thermal cycle test.

Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique

A delay-compensation circuit for low-power subthreshold digital circuits is proposed. Delay in digital circuits operating in the subthreshold region of MOSFETs changes exponentially with process and temperature variations. Threshold-voltage monitoring and supply-voltage scaling techniques are adopted to mitigate such variations. The variation in the delay can be significantly reduced by monitoring the threshold voltage of a MOSFET in each LSI chip and exploiting the voltage as the supply voltage for subthreshold digital circuits. The supply voltage generated by the threshold voltage monitoring circuit can be regarded as the minimum supply voltage to meet the delay constraint. Monte Carlo SPICE simulations demonstrated that a delay-time variation can be improved from having a log-normal to having a normal distribution. A prototype in a 0.35-µm standard CMOS process showed that the exponential delay variation with temperature of the ring-oscillator frequency in the range from 0.321 to 212kHz can remain by using compensation in the range from 5.26 to 19.2kHz.

チップ試作とIPデータベースを導入したLSI設計教育

Recently, FPGA chips are sometimes used instead of fabricating LSI chips in the LSI design education. However the inside of FPGA chip is sometimes regarded as a black box and it is not connected to the knowledge of MOS FET and CMOS gate structures in the field of semiconductor processes. In Graduate School of Engineering, Hiroshima Institute of Technology, we have been teaching “Advanced System Development Technology of Integrated Circuits” as a coursework. Since 2009, we have introduced a prototype chip into the coursework where students draw layouts of half adder, full adder, and 2-bit adder in order to understand the relation between the areas of semiconductor processes and LSI design. The fabricated chip is verified by using logic analyzer. In addition to this, we have introduced an IP database into the coursework, where IP means circuit diagrams or circuits written in hardware description language which are already designed and verified. In order to refer the circuits written in a various descriptions such as VHDL, circuit diagram, etc., we collected those IP, constructed an IP database, and introduced into the coursework. By the questionnaire survey, the effectiveness of both prototype chip and IP database is verified.

Low Power Platform for Embedded Processor LSIs

Various low power technologies have been developed and applied to LSIs from the point of device and circuit design. A lot more CPU cores as well as function IPs are integrated on a single chip LSI today. Therefore, not only the device and circuit low power technologies, but software power control technologies are becoming more important to reduce active power of application systems. This paper overviews the low power technologies and defines power management platform as a combination of hardware functions and software programming interface. This paper discusses importance of the power management platform and direction of its development.

CAT (Critical-Area-Targeted): A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing

At-speed scan testing is essential in guaranteeing LSI chip quality in the deep-submicron era; however, chip/package damage, yield loss, and reliability degradation may occur in at-speed scan testing due to excessive test power, which can be several times higher than functional power. This problem is especially severe for low-power devices. In this paper, the background of the test power problem is reviewed, and the characteristics of two different types of test power (shift and capture) are highlighted. Then, a general strategy for test power reduction is described. After that, information on a novel CAT (critical-area-targeted) technique for tackling the more challenging problem of capture power reduction is provided. This unique and sophisticated technique can effectively reduces launch switching activity in a pinpoint manner by targeting at areas around long sensitized paths (called critical areas). Evaluation results on industrial circuits demonstrate the need for such CAT techniques.

Nondestructive Warpage Measurements of LSI Chips in a Stacked System in Package by Using High-Energy X-ray Diffraction

We describe high-energy X-ray diffraction to examine the warpage of packaged LSI chips nondestructively. Less absorption of the high-energy X-rays enables us to observe diffracted X-rays through packaging materials and LSI chips. We demonstrate that it is possible to measure the warpage of LSI chips in a stacked system in package (SiP). Although an LSI chip in a single-chip ball grid array (BGA) package simply warps into a convex-down shape, the LSI chips packaged in the BGA package as a stacked SiP warp into the shape of waves. It is inferred from results of our examination that the stress due to a printed circuit board substrate and molding resin affects chip warpage.

Multichannel Biosensing and Stimulation LSI Chip Using 0.18 µm Complementary Metal–Oxide–Semiconductor Technology

We designed 8-channel preamplifiers and multisite stimulation circuits on a 2.5 ×1.4 mm2 chip using a 0.18 µm complementary metal–oxide–semiconductor (CMOS) process for a microelectrode array measurement system. The size of a 1-channel preamplifier including a DC store/adder circuit is 930 ×120 µm2. An 8-channel programmable stimulator was integrated on the same die. The preamplifier circuits can amplify a small neural signal with a low noise and a low power consumption (2 mW/ch) using a chopper operation. The stimulation circuits can apply a voltage of ±700 mV to any channel and with any timing using serial digital data control. The performance of the biphasic stimulation waveform generated by the designed LSI chip is the same as that generated with a conventional stimulation system. These functions were confirmed by connecting the LSI chip to a conventional measurement system. The system miniaturization achieved using the custom LSI chip will offer great advantages in terms of future brain machine interface applications.

Three-Dimensional Binocular Range Sensor LSI with Enhanced Correlation Signal

We developed a three-dimensional (3D) binocular range sensor LSI with an enhanced correlation signal. The developed LSI chip was produced using a process of 0.35 µm complementary metal oxide semiconductor (CMOS) 1-poly 3-metal and has a die size of 4.20×3.33 mm2. The chip uses a 3.0 V supply voltage and has a power consumption of 280 mW at a clock frequency of 10 MHz. Two image sensors and the circuits for binocular stereo vision are integrated into the sensor. The distance to an object is determined by calculating the correlation between the two photosensors' output differential signals and observing the position of strong correlated values. However, in the previously developed range sensor, the correlation was weak when there was a small differential signal and it was unable to simultaneously detect several objects. In the newly developed range sensor, a circuit that modulates the differential signal was integrated and the correlation process was enhanced. The object detection signals are ten times larger than those of the previous sensor. As a result, we were able to simultaneously detect the 3D position of several objects. All the necessary calculations for 3D detection take 32 µs per frame. However, the output time for one 3D frame is 26 ms. Thus, the frame rate is limited to 38 frames per second.

Warpage Mechanism of Thin Embedded LSI Packages

The warpage mechanism of a thin embedded LSI package with a thick Cu plate was investigated for various Cu plate thicknesses. The package warpage increased gradually as the Cu plate was made thinner. Even structures with a balanced Cu and resin layer configuration for the top and bottom portions of the embedded chip showed substantial warpage, especially in the chip region, that was greater than that for an unbalanced layer configuration. This indicates the existence of other warpage factors as well as unbalanced residual stress between the top and bottom of the chip. A `Birth & Death' finite element method simulation showed that the thermal residual stresses induced by the coefficient of thermal expansion mismatch for the LSI chip and embedding resin were concentrated in the resin surrounding the lateral sides of the chip and that the stresses increased with decreasing Cu thickness. The release of these tensile stresses resulted in package warpage.

A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI

The energy dissipation by data communications on a LSI chip depends on the layout of modules as well as how data are communicated among modules. The requirement of data communications are determined by the schedule of computations and by the resource binding of computations to functional units and data to registers. In this paper, a method of resource binding is proposed to derive a binding which is able to obtain the floorplan with reduced energy dissipation by data communications.

Novel interconnection technology for heterogeneous integration of MEMS–LSI multi-chip module

We developed novel interconnection technology for heterogeneous integration of MEMS and LSI multi-chip module, in which MEMS and LSI chips would be horizontally integrated on substrate and vertical...

Novel interconnection technology for heterogeneous integration of MEMS–LSI multi-chip module

We developed novel interconnection technology for heterogeneous integration of MEMS and LSI multi-chip module, in which MEMS and LSI chips would be horizontally integrated on substrate and vertically stacked each others. The cavity chip composed of deep Cu TSV-beam lead interconnections was developed for interconnecting MEMS chips with high step height of more than few hundreds micrometer without the degradation of sensing elements. Fundamental characteristics were successfully obtained from pressure sensing MEMS chip with 360 μm thickness, which was connected to Si substrate by the cavity chip. MEMS and LSI chips were vertically integrated by using the cavity chip without any changing of chip design and extra processes. This interconnection technology can give strong solution for heterogeneous integration of MEMS and LSI chips multi-chip module.

Laser THz emission microscope as a novel tool for LSI failure analysis

We have proposed and developed a novel technique for a non-contact inspection of defective interconnections in an LSI chip using a laser terahertz emission microscope (LTEM). The LTEM measures the THz emission images of an LSI chip by scanning it with fs laser pulses. When a fs laser pulse irradiates a p–n junction in an LSI chip, transient photocurrent flows into interconnections resulting in the emission of the THz pulse into free space. We investigated the characteristics of the THz emissions from simple test element group samples which consist of p–n junctions connected to metal lines. It was found that the metallic lines connected to photo-excited p–n junctions worked as THz emission antennae which enhance the emission efficiency of THz pulses near their resonant frequencies corresponding to the line lengths. This result indicates that THz emission signals from p–n junctions in circuits strongly depend on the structure of the interconnections. We show the successful results on the inspection of defective interconnections in MOSFET devices and C7552 ISCAS’85 benchmark circuits using LTEM. By comparing the THz emission images between a normal circuit and a defective one, it is possible to identify the p–n junctions connected to the defective interconnections without electrical contacts.

Boiling Heat Transfer Enhancement by Using Micro-pin-finned Surface for Electronics Cooling

For efficiently cooling electronic components with high heat flux, experiments were conducted to study the flow boiling heat transfer performance of FC-72 over square silicon chips with the dimensions of 10 × 10 × 0.5 mm3. Four kinds of micro-pin-fins with the dimensions of 30 × 60, 30 × 120, 50 × 60, 50 × 120 μm2 (thickness, t × height, h) were fabricated on the chip surfaces by the dry etching technique for enhancing boiling heat transfer. A smooth surface was also tested for comparison. The experiments were made at three different fluid velocities (0.5, 1 and 2 m/s) and three different liquid subcoolings (15, 25 and 35 K). The results were compared with the previous published data of pool boiling. All micro-pin-fined surfaces show a considerable heat transfer enhancement compared with a smooth surface. Flow boiling can remarkably decrease wall superheat compared with pool boiling. At the velocities lower than 1 m/s, the micro-pin-finned surfaces show a sharp increase in heat flux with increasing wall superheat. For all surfaces, the maximum allowable heat flux, q max , for the normal operation of LSI chips increases with fluid velocity and subcooling. For all micro-pin-finned surfaces, the wall temperature at the critical heat flux (CHF) is less than the upper limit for the reliable operation of LSI chips, 85°C. The largest value of q max can reach nearly 148 W/cm2 for micro-pin-finned chips with the fin height of 120 μm at the fluid velocity of 2 m/s and the liquid subcooling of 35 K. The perspectives for the boiling heat transfer experiment of the prospective micro-pin-finned surfaces, which has been planned to be made in the Drop Tower Beijing/NMLC in the future, are also presented.

Development of Si Double-Sided Microelectrode for Platform of Brain Signal Processing System

We have proposed a new implantable neural recording system, which we call the brain signal processing system (BSPS). In this system, LSI chips such as amplifiers, analog-to-digital converters, and multiplexers are integrated on the Si microelectrode array. To analyze the brain functions or to develop medical treatments for brain disorders, a high-density recording of action potentials is strongly required. To realize high-density recording of action potentials, we propose a novel Si double-sided microelectrode that has recording sites on both front and back sides. The back-side recording sites are connected to a recording apparatus by wire bonding through Si via holes. We fabricated the carefully designed Si double-sided microelectrode and evaluated the electrical characteristics of the Si microelectrode. The front- and back-side recording sites had impedance values of 2.5 and 2.7 MΩ at 1 kHz, respectively, which indicated that both recording sites have equivalent characteristics. An in vitro experiment of neuronal action potential recording using the fabricated Si double-sided microelectrode was performed. The CA1 areas of 400-µm-thick hippocampal slices obtained from the brains of guinea pigs were employed, and we successfully recorded neuronal action potentials from the recording sites of both sides.

Optical Interposer Technology using Buried Vertical-Cavity Surface-Emitting Laser Chip and Tapered Through-Silicon Via for High-Speed Chip-to-Chip Optical Interconnection

A novel optical interposer with optical interconnections is proposed for integrating three-dimensional (3D) LSI chips on this interposer. Vertical-cavity surface-emitting laser diode (VCSEL) chips and photo diode (PD) chips are buried in the optical interposer with polymeric optical waveguides. The VCSEL is 0.25 mm in width, 0.35 mm in length, and 0.15 mm in height. We realize precise passive alignment between the optical waveguides and the VCSEL/PD chips using two-step alignment processes consisting of cavity-assisted positioning and the subsequent surface-tension-powered self-assembly with a molten solder. In addition, we demonstrate the basic operation of the buried VCSEL chips in the optical interposer through tapered through-silicon vias (TSVs). The tapered TSVs are successfully formed by copper electroplating and are 64 µm in top width, 34 µm in bottom width, and 168 µm in length.

Enhanced flow boiling heat transfer of FC-72 on micro-pin-finned surfaces

For the purpose of cooling electronic components with high heat flux efficiently, some experiments were conducted to study the flow boiling heat transfer performance of FC-72 on silicon chips. Micro-pin-fins were fabricated on the chip surface using a dry etching technique to enhance boiling heat transfer. Three different fluid velocities (0.5, 1 and 2 m/s) and three different liquid subcoolings (15, 25 and 35 K) were performed, respectively. A smooth chip (chip S) and four micro-pin-finned chips with the same fin thickness of 30 μm and different fin heights of 60 μm (chip PF30–60) and 120 μm (chip PF30–120), respectively, were tested. All the micro-pin-finned surfaces show a considerable heat transfer enhancement compared to the smooth one, and the critical heat flux increases in the order of chip S, PF30–60 and PF30–120. For a lower ratio of fin height to fin pitch and/or higher fluid velocity, the fluid velocity has a positive effect on the nucleate boiling curves for the micro-pin-finned surfaces. At the velocities lower than 1 m/s, the micro-pin-finned surfaces show a sharp increase in heat flux with increasing wall superheat, and the wall temperature at the critical heat flux (CHF) is less than the upper limit, 85 °C, for the reliable operation of LSI chips. The CHF values for all surfaces increase with fluid velocity and subcooling. The maximum CHF can reach nearly 150 W/cm 2 for chip PF30–120 at the fluid velocity of 2 m/s and the liquid subcooling of 35 K.

New Approach of Laser-SQUID Microscopy to LSI Failure Analysis

We have proposed and successfully demonstrated a two step method for localizing defects on an LSI chip. The first step is the same as a conventional laser-SQUID (L-SQUID) imaging where a SQUID and a laser beam are fixed during LSI chip scanning. The second step is a new L-SQUID imaging where a laser beam is stayed at the point, located in the first step results, during SQUID scanning. In the second step, a SQUID size (A eff ) and the distance between the SQUID and the LSI chip (ΔZ) are key factors limiting spatial resolution. In order to improve the spatial resolution, we have developed a micro-SQUID and the vacuum chamber housing both the micro-SQUID and the LSI chip. The A eff of the micro-SQUID is a thousand of that of a conventional SQUID. The minimum value of ΔZ was successfully reduced to 25 μm by setting both the micro-SQUID and an LSI chip in the same vacuum chamber. The spatial resolution in the second step was shown to be 53 μm. Demonstration of actual complicated defects localization was succeeded, and this result suggests that the two step localization method is useful for LSI failure analysis.

Application of the Wire Bonding Technology to a Flexible Neural Probe

This paper proposes a novel neural probe using flexible metal wire for wire bonding on LSI chip. Wire bonding technology can provide a number of flexible wire arrays. The proposed neural probe is used for a nerve interface for functional electric stimulation (FES) technology which assists the paralysis of living body function by a spinal cord injury. The flexibility of probe will provide low invasive and safe neural interfaces for the nerve tissue from a long term view. We employ a combination of wire bonding and laser machining for the fabrication of aligned flexible probes. Aligned bonded flexible metal wires on electrodes are converted to probe arrays by cutting the bridge between electrodes. Typical dimension of a bonding wire is several tens μm in diameter and is suitable for neural probe to be inserted into nerve bundles. Needle shape is formed by electro-polishing of cut edge. Proposed method can be benefited by advantages of wire bonding as the widespread technology in electronics industry. Developed flexible neural probe based on the proposed technology is estimated as a nerve interface by inserting to a sciatic nerve of a rat.