Low On-state Resistance Research Articles

RETRACTED ARTICLE: Modified SVPWM based three phase to nine phase matrix converter for nine phase induction motor with closed loop speed control

A new design procedure is presented in this paper to simulate the implementation of 3–9 Ф power conversion using matrix converter whose output is fed to the Induction motor to control speed under closed loop configuration. Using mathematical derivations, the converter is modeled and its performance is evaluated using nonlinear load. The overall matrix converter circuit is simulated in MATLAB. The numerical equations which relate the input and outcome of the 9Ф matrix converter is executed by utilizing Simulation blocks. The duty cycle of the bidirectional switches is estimated using PI/PR/Fuzzy controller for optimum voltage transfer ratio. Due to the low on-state resistance and conduction losses, and better power handling capacity in addition to the ability of switching at higher voltages at frequency below 20 kHz, the power circuit was implemented using bidirectional IGBT switches to achieve high speed switching operation (10 kHz) and to minimize on state conduction misfortunes with less THD. The duty cycle of the bidirectional switches are controlled by the space vector PWM controller. Finally the performance of the controllers is compared with regards to THD.

An extended high-voltage-gain DC–DC converter with reduced voltage stress on switches/diodes

A new transformer-less boost-based DC–DC converter is suggested in this research. The voltage gain of the proposed converter is enhanced employing a charge-pump circuit (CPC) and n-stages of voltage multiplier cells (VMC). Each VMC consists of one inductor, one diode, and two capacitors. As the number of these VMC stages (n) increases, it is feasible to achieve high voltage gains with low duty cycles. Furthermore, by expanding n, a significant reduction of the normalized peak voltage stress (NPVS) of the components is possible. Due to this feature, using the MOSFET switches with low ON-state resistance and the low-rating voltage components is provided which results in diminishing the conduction and switching losses. The steady-state analysis is accomplished in details and the comparison considering other converters in the literature is presented in this manuscript. Validating of the converter performance is accomplished by implementing a laboratory prototype for the power of 300 W, input, and output voltages of 30 V and 310 V, respectively, and switching frequency of 40 kHz. Experimental results validate the mathematical analysis.

A Novel ZVS High-Step-Up Converter With Built-In Transformer Voltage Multiplier Cell

This article proposes a novel interleaved high-step-up dc-dc converter with zero voltage switching (ZVS). Through a built-in transformer voltage multiplier cell (VMC) the high voltage conversion ratio is achieved without the narrow duty. By applying active clamp scheme, all of the power MOSFETs are switched with ZVS which minimizes the switching losses of the proposed converter. Besides the voltage stress across the switches is decreased and can be controlled by the built-in transformer turns ratio enabling utilization of low on-state resistance and low forward voltage drop semiconductors. Due to the interleaved structure, the input current ripple is minimized and the thermal stress is shared between the phases. Meanwhile, the charge balance of the capacitors give rise to equal current sharing performance for the two input inductors. All of these factors reduce the power losses and improves the performance of the proposed converter. Finally, in order to verify the operation of the proposed converter, a 35-V input voltage to 500-V output voltage prototype with the rated power of 1 kW is fabricated and tested in the laboratory.

Interleaved High Step-Up DC–DC Converter with Voltage-Lift and Voltage-Stack Techniques for Photovoltaic Systems

A novel interleaved high step-up DC–DC converter applied for applications in photovoltaic systems is proposed in this paper. The proposed configuration is composed of three-winding coupled inductors, voltage multiplier cells and a clamp circuit. The step-up voltage gain is effectively increased, owing to the voltage-stack and voltage-lift techniques using the voltage multiplier cells. The leakage inductor energy is recycled by the clamp circuit to avoid the voltage surge on a power switch. The low-voltage-rated power switches with low on-state resistances and costs can be used to decrease the conduction losses and increase the conversion efficiency when the voltage stresses of power switches for the converter are considerably lower than the high output voltage. The reverse-recovery problems of diodes are mitigated by the leakage inductances of the coupled inductors. Moreover, both the input current ripple and the current stress on each power switch are reduced, owing to the interleaved operation. The operating principle and steady-state analysis of the proposed converter are thoroughly presented herein. A controller network is designed to diminish the effect of the variations of input voltage and output load on the output voltage. Finally, the experimental results for a 1 kW prototype with 28–380 V voltage conversion are shown to demonstrate its effectiveness and performance.

A Novel Interleaved High Step-Up Converter With Built-In Transformer Voltage Multiplier Cell

In this article, we propose a novel interleaved high step-up converter. The proposed converter integrates the built-in transformer voltage multiplier cell (VMC) to the interleaved boost converter with voltage lift capacitor. The voltage gain is increased by both of the turns ratio of the built-in transformer and the voltage lift capacitor. Hence, there is no need to operate the converter around unity duty cycles to obtain high voltage gains. Meanwhile, the voltage stress across semiconductors is reduced considerably, facilitating the utilizing of mosfets with low on-state resistance and diodes with low forward voltage drop decreasing the conduction losses. The leakage inductance of the built-in transformer not only provides zero current switching (ZCS) for mosfets but also controls the falling current rate of the diodes alleviating the reverse current recovery problem. In addition, the energy of the leakage inductance is recycled by the clamp capacitor avoiding high spikes across switches. In comparison with the recently published converters, the proposed converter introduces all of the abovementioned advantages with a low number of components that make it an interesting solution for high efficiency and high step-up applications. Finally, a 40-V to 580-V prototype with 930 W power is fabricated to explore the merits of the proposed converter.

III-N heterostructures for monolithic integration of enhancement/depletion-mode high-electron-mobility transistors

Simulation analysis of III-N two-dimensional electron gas-based structures that could be used for stable monolithically integrated enhancement/depletion-mode circuits was carried out. Three different designs were proposed and analysed, including a novel p-GaN/AlN-GaN SPSL/GaN, which is expected to have lower ON-state resistance and higher transconductance than conventional normally-off GaN-based transistors.

A Hybrid Cascaded High Step-Up DC–DC Converter With Ultralow Voltage Stress

A novel hybrid cascaded dc–dc converter is proposed for high voltage gain applications in this article, which is characterized by the hybrid series-parallel connection based on coupled inductors and voltage multiplier cells. The input current ripple is decreased due to the interleaved operation and the voltage stress of the switches is only 1/6 of the output voltage when the turn ratio is 1. So the high-performance MOSFETs with low ON-state resistance can be used to reduce the conduction losses. The reverse-recovery problem of the output diode can be suppressed by the leakage inductance of the coupled inductors. The leakage inductance energy of the coupled inductors is absorbed and recycled to the output, which can largely improve the efficiency of the proposed converter. The working principle and steady-state characteristics of the converter are analyzed in detail. Finally, the correctness of the theoretical analysis is verified through experimental results of a 400-W laboratory prototype.

The Influence of Anode Trench Geometries on Electrical Properties of AlGaN/GaN Schottky Barrier Diodes

AlGaN/GaN lateral Schottky barrier diodes (SBDs) with three different anode geometries (stripe, circular, and the conventional plane one) and different rows of anode trenches are fabricated and electrically characterized to study the influence of anode trench geometries. The SBDs with anode trenches exhibit the lower on-state resistance (RON) than that with the conventional plane one. It can be explained that the anode trenches made the Schottky metal directly contact to the 2DEG at the sidewall of the AlGaN/GaN interface, removing the AlGaN barrier layer in the conventional plane anode. In addition, the RON of the SBDs with circular trenches is smaller than that of the SBDs with stripe ones. Furthermore, the RON decreases with the increasing rows of anode trenches, which can be attributed to the increased contact area between the Schottky metal and the 2DEG. For the reverse characteristics, the anode trenches do not lead to performance degradation. The fabricated devices exhibit the low reverse current (IR, IR < 1 μA/mm), and the breakdown voltage (VBK) remains unchanged with different anode geometries.

Two‐ and three‐winding coupled‐inductor‐based high step‐up DC–DC converters for sustainable energy applications

This study proposes two configurations for a non-isolated, high step-up, single-switch, coupled-inductor-based DC–DC converter. A coupled inductor and voltage multiplier cells are used in the presented topologies to obtain a high voltage gain. Also, a passive clamp circuit is applied in the topologies to reduce voltage stress of the main power switch. This leads to utilising a power switch with lower on-state resistance, which decreases the conduction loss. Several advantages such as low operating duty cycle, high voltage conversion ratio, reduced voltage stress of semiconductors, low turn ratio of the coupled inductor, leakage inductance energy recovery and high efficiency operation make the presented structures appropriate for sustainable energy applications. The operational principle and steady-state analysis of the suggested topologies in continuous conduction mode are expressed in detail. Also, design procedure and theoretical efficiency of the topologies are presented. Then, the suggested topologies are compared with several similar high step-up topologies to prove their advantages. Finally, the performance and feasibility of the proposed DC–DC converter configurations are confirmed through experimental measurement results of 29 V input and 435 V/213 W and 480 V/238 W output laboratory prototypes at 50 kHz switching frequency.

Cost-Effective Matrix Rectifier Operating With Hybrid Bidirectional Switch Configuration Based on Si IGBTs and SiC MOSFETs

For so many years, silicon (Si) IGBTs have been widely utilized in power converters for low-to-medium voltage high-power applications. However, the ever-increasing requirements to improve power density, power quality, and efficiency of power converters have urged researchers to explore alternative technologies such as silicon-carbide (SiC) MOSFETs. SiC devices fill the mentioned gaps with increased voltage blocking capability, higher switching speed, and lower on-state resistance; yet, their price is much more elevated. Both technologies are adopted in matrix rectifiers (MRs), which have recently gained attention for on-board electric vehicle (EV) charger and battery energy storage system (BESS) applications because of their controllable bidirectional power flow and compact size. A MR contains bidirectional switches made up of two power devices, doubling the device count and cost to conventional voltage source converters (VSCs). In this paper, we compare in terms of efficiency four types of MRs, each one consisting of a specific bidirectional switch configuration. Among these switches, we propose a cost-effective hybrid configuration consisting of Si IGBTs and SiC MOSFETs for straightforward commutations during the charging mode of matrix rectifiers. Also, the proposed configuration is compared to other typical bidirectional switch configurations. To perform these comparisons, the switching energy losses in 1200 V commercial IGBTs and MOSFETs, constituting the bidirectional switches, are measured through the double-pulse test (DPT). Performance comparisons of the MRs are supported through a simulator and verified via experimental work, where the proposed arrangement results in a cost-effective solution in MRs operating with switching frequencies up to 50 kHz and further.

Normally-off p-GaN Gated AlGaN/GaN HEMTs Using Plasma Oxidation Technique in Access Region

Normally-off p-GaN gated AlGaN/GaN high electron mobility transistors (HEMTs) were developed. Oxygen plasma treatment converted a low-resistive p-GaN layer in the access region to a high-resistive GaN (HR-GaN); that oxygen plasma treatment used an AlN layer as an oxygen diffusion barrier layer to prevent further oxidizing of the underlying AlGaN barrier layer, and to ensure that the low-resistive p-GaN layer in the access region was fully oxidized. Relative to conventional p-GaN gated AlGaN/GaN HEMTs, these AlGaN/GaN HEMTs with HR-GaN layers achieved a lower drain leakage current of 4.4 x 10 -7 mA/mm, a higher drain current on/off ratio of 3.9 x 10 9 , a lower on-state resistance of 17.1 Ω·mm, and less current collapse.

Design and Fabrication of Ion-Implanted Moat Etch Termination Resulting in 0.7 m$\Omega\cdot$ cm2/1500 V GaN Diodes

The design space of ion-implanted moat etch termination in GaN p-n diodes is discussed in this study. Based on experimental data, the design window for ion-implanted moat etch termination has been carefully studied and optimized for vertical GaN p-n diodes grown on bulk GaN substrates. A high-performance diode with a breakdown voltage of 1500 V and a low specific on-state resistance of 0.7 $\text{m}\Omega \cdot $ cm2 is demonstrated using the optimized edge termination based on moat etch and Mg ion implantation. The p-n diode shows a device figure-of-merit of 3.2 GW/cm2. By using the proposed ion-implanted moat etch termination, GaN diodes with three different drift region designs approach the avalanche breakdown electric field, which indicates the efficacy of the proposed edge termination design and method.

Comparative efficiency analysis for silicon, silicon carbide MOSFETs and IGBT device for DC–DC boost converter

In present study, a comparative efficiency analysis for silicon (Si), silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistor (IGBT) device based DC–DC boost converter is performed. Due to different gate-drive characteristics of power semiconductor devices such as Si, SiC MOSFETs and IGBT device, different voltage levels are required to drive aforementioned devices. A 500 W boost converter for wide input voltage range (30–72 V) and 110 V output voltage is designed having a single gate driver circuit for Si, SiC MOSFETs and IGBT. A single gate driver provides the gate-source (or base-emitter in case of IGBT) signal for all the devices which eliminates the use of separate gate driver circuit. Si MOSFET and IGBT are driven by 12 V gate-source voltage whereas SiC MOSFET is operated by 18 V gate-source voltage using the gate driver circuit. An experimental study is performed for the comparative efficiency analysis for Si, SiC MOSFETs and IGBT device based converter for 20 and 50 kHz switching frequencies. It is found that SiC based converter provides highest efficiency ≈ 97.8%, whereas the lowest efficiency ≈ 94% is found for IGBT based converter at 20 kHz switching frequency. SiC based converter gives higher efficiency because lower conduction loss owning to lower on-state resistance as compared to Si MOSFET. Besides this, SiC application has another advantage such as low switching loss at higher frequency resulting compact size of converter. However, use of IGBT at higher switching frequency results in higher switching losses, hence lower efficiency of the converter.

A High Voltage Gain DC–DC Converter Based on Three Winding Coupled Inductor and Voltage Multiplier Cell

This article introduces a single-switch, high step-up, dc–dc converter based on coupled-inductor with three winding and voltage multiplier cell to obtain a very high-voltage conversion ratio. A passive clamp circuit is applied in the converter to recycle the energy of leakage inductance and reduce voltage stress of the main power switch. This leads to utilize a power switch with low on-state resistance and low voltage rating that decreases the conduction losses. Several advantages include low operating duty cycle, high voltage conversion ratio, low turn ratio of the coupled inductor, leakage inductance reverse recovery, reduced voltage stress of semiconductors, alleviation of diodes reverse recovery issue and high efficiency, which make the presented topology appropriate for sustainable energy applications such as photovoltaic systems. The operation principle and steady-state analysis of the suggested topology in continuous conduction mode are expressed in detail. Also, design procedure and theoretical efficiency analysis of the proposed topology are presented. Moreover, a comparison study is performed to demonstrate the superiority of the presented converter over several similar recently proposed dc–dc converters. Finally, the proposed dc–dc converter feasibility and performance are justified through a fabricated 216-W laboratory prototype at 50 kHz switching frequency.

Experimental Characterization of Silicon and Gallium Nitride 200 V Power Semiconductors for Modular/Multi-Level Converters Using Advanced Measurement Techniques

The increasing demand for higher power densities and higher efficiencies in power electronics, driven by the aerospace, electric vehicle, and renewable energy industries, encourages the development of new converter concepts. In particular, modular and/or multi-level (M/ML) topologies are employed to break the performance barriers of the state-of-the-art power converters by simultaneously reducing the system losses and volume/weight. These improvements mainly originate from the replacement of high-voltage transistors, typical of two-level converters, with low-voltage, e.g., 200 V, devices, offering superior electric performance. Hence, two low on-state resistance silicon (Si) and gallium nitride (GaN) 200 V power semiconductors are comprehensively characterized in this article to support the multi-objective optimization and the design of M/ML power converters. First, the selected devices are analyzed experimentally determining their conduction, thermal, and switching characteristics; for this purpose, a novel ultra-fast transient calorimetric measurement method is introduced and explained in detail. In the course of this analysis, an unexpected switching loss mechanism is observed in the Si devices at hand; the physical reason of this behavior is clarified and it is proven to be solved in the next-generation research samples, which are also characterized by measurements. Finally, the influence of the measured power semiconductors’ performance on the overall efficiency and power density of a typical converter is determined through a case study analyzing a hard switching half-bridge operated as a single-phase inverter, i.e., the fundamental building block of several M/ML topologies. It is concluded that, in this voltage and power class, GaN e-FETs are nowadays approximately a factor of three superior to Si power MOSFETs; however, the better heat dissipation achieved by the latter still makes them the preferred solution for higher power applications.

Numerical analysis of high‐voltage RESURF AlGaN/GaN high‐electron‐mobility transistor with graded doping buffer and slant back electrode

A reduced surface field (RESURF) AlGaN/GaN high-electron-mobility transistor (HEMT) with graded doping buffer (GDB) and slant back electrode (SBE) is proposed. In the GDB, the p-dopant density increases linearly both from top to bottom and right to left. The concentrated negative space charges in the lower-left corner of GDB attract the electric field lines from the channel and barrier towards the gate under OFF-state, which flats the electric field and enhances the breakdown voltage ( V br ). Additionally, the low p-dopant density near the top of GDB achieves the device with low ON-state resistance ( R ON ). The SBE flats the electric field along the channel above it and introduces a peak electric field near its edge. Simulation results show a V br of 2150 V and R ON of 7.05 Ωmm for the proposed device, compared with 1701 V and 7.73 Ωmm for the conventional back electrode RESURF HEMT (BE-RESURF HEMT) with the same gate -drain spacing. Moreover, due to the reduced depletion of 2DEG from the GDB, the proposed device shows slight increases in f T and f max (8.76 and 14.80 GHz), comparing with the conventional BE-RESURF HEMT (8.24 and 13.84 GHz).

Gate Drivers for High-Frequency Application of Silicon-Carbide MOSFETs: Design considerations for faster growth of LV and MV applications

With the advent of wide-bandgap (WBG) semiconductor devices, silicon-carbide (SiC)-based MOSFETs for high voltage and current serve as a viable replacement for conventional Si-based IGBTs [1], [2]. SiC-based MOSFETs combine the advantages of both IGBTs and MOSFETs, have a low on-state resistance at a high-voltage rating (similar to IGBTs), and lower-switching losses than those of Si MOSFETs, thus making it closer to an ideal switch [3]. This makes it possible for SiC MOSFETs to process high power at high-switching frequencies without compromising the efficiency of the system [4]. Due to the inherent lower on-state specific resistance and faster switching speeds in SiC MOSFETs, it is also possible to develop and use medium-voltage (MV) power semiconductor devices greater than 6.5 kV without experiencing very high losses [5]. The SiC MOSFET design and development can be divided into two broad categories: low-voltage (LV)-blocking (l3.3-kV) and MV-blocking (g3.3-kV) SiC MOSFETs [6]. Although MV SiC MOSFETs can enable niche applications, there is widespread use of LV-blocking power devices in various applications such as renewable energy, drives for electrical machines, power converters for electric vehicles, and so on, whereas SiC MOSFETs can offer a multitude of advantages over Si IGBTs [7], [8].

(Invited) Reliability Considerations for Al-Rich Aluminum Gallium Nitride Power Switching Transistors

High breakdown voltage and low on-state resistance are important factors that have enabled improved performance and efficiency of power switching transistors. Based on wide-bandgap (WBG) semiconductors, these transistors have recently entered commercial applications. The next generation of power transistors utilize a new class of semiconductor materials with bandgaps (Eg ) greater than that of GaN (3.4 eV), the “ultra” wide-bandgap (UWBG) semiconductors, Eg = 3.4 – 6.2 eV [1-3]. In particular, Al-rich AlGaN alloys and b-Ga2O3 represent two UWBG semiconductors with considerable recent interest [2,3]. The large bandgap of an UWBG semiconductor is an important factor in determining the critical electric field (EC , scaling as approximately as Eg 2.5 [2]), which not only affects breakdown, but also confers operability advantages in harsh environments embodied by 500°C temperatures [4]. We will discuss the progress and challenges for maturing the Al-rich AlGaN transistors (the percent of Al approaches 100%, e.g. AlN) to the point where they represent viable technology choices for extreme environments, and perhaps more broadly. After presenting the highlights of the Al-rich transistor research, attention will be given to reliability considerations, which are motivated by the ability to influence early technology decisions. Thus, the purpose of reliability research into emerging technologies is to provide early data that impacts material and process choices for the Al-rich transistors and not to attempt reliability determinations, per se. Step-stress experiments are one of the main tools available for undertaking early reliability analysis. Examples of both enhancement-mode [5] and depletion-mode HEMT step-stress experiments will be described and analyzed. Such experiments allow quick examination of multiple types of stress, including, those absent of drain current and those with varying concentrations of hot electrons, all while sampling progressively increasing magnitude of gate- or drain-bias derived electric fields. In this manner, one discovers parametric boundaries affecting degradation and may identify the most relevant follow-up experiments. Step-stress experiments may involve both reversible parametric effects and permanent ones. The reversible effects are those that heal or re-occur with abrupt changes in bias conditions and are associated with carrier capture and emission processes. They have the potential to confound the reliability analysis because considerable parametric changes can be observed. They must be accounted for so that proper interpretation of potential degradation is made. They also have the potential to reveal important details of how the capture and emission processes affect device operation. Although many examples of these experiments will highlight parallels with conventional AlGaN/GaN transistors, some notable differences unique to Al-rich semiconductors will be described as well. [1] J.Y. Tsao et al., Advanced Electronic Materials, 4, 1600501 (2018). [2] R. J. Kaplar et al., ECS J. Solid State Science and Technology, 6, Q3061 (2017). [3] M. Higashiwaki and G. H. Jessen, Appl. Phys. Lett. 112, 060401 (2018). [4] P. H. Carey et al., J. Electron Devices Society, 7, 444 (2019). [5] A.G. Baca et al., Int. Reliability Physics Symp., P.WB.2 (2019). This work was supported by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. The views expressed in the presentation do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

(Invited) Nanostructures and Crystal Defects in Thick GaN and SiC Epitaxial Layers for Power Electronic Switches

The state-of-the-art power switching devices made from SiC and GaN semiconductors contain a high density of crystal defects. Most of these defects are present in starting wafers and some are generated during device processing. There is little conclusive evidence so far on the exact role that the crystal defects play on device performance, manufacturing yield, and more importantly, long-term field-reliability especially when devices are operating under extreme stressful environments. This paper provides a review of the current state-of-the-art of SiC and GaN power semiconductor material technology, and the potential impact crystal defects may have on high-density power switching electronics. Group III-Nitride materials suffer from both extended and point defects, each of which will challenge the material’s application in both vertical and lateral power devices. The extended defects include vertical threading dislocations of both edge and screw type. The latter defects have been shown to be correlated to leakage in vertical two terminal device structures while the influence of the former is still undetermined and remains a critical research issue. Channel surfaces in vertical three terminal devices will also degrade due to vertical threading dislocations. These extended defects occur in all epitaxial layers grown on c-plane substrates (the predominant and largest area substrate type) and are the result of the lack of a high quality substrate bulk material as well as substrate surface. The present substrate technology after multiple efforts (either GaN, SiC or Si) still have a high defect density indicating that low-defect seeds may be non-existing. Point defects influence the background carrier concentration in low-doped layers and various recombination processes. The intrinsic nature of III-N materials makes nitrogen-vacancies a predominant point defect that automatically dopes the crystal n-type, but there are impurities (oxygen and carbon) from most growth environments that also contribute to conductivity. These defects are not well understood and not well controlled. Such defects must be minimized in order to realize thick epitaxial layers with drift regions that will support both high blocking voltages and low on-state resistances. A wide range of materials characterization methods have been applied to further understand these impurities. The semiconductor and dielectric materials used in the construction of power electronics switching devices employed for energy efficiency applications experience extreme electrical and thermal stresses during the on-state as well as when switching high voltages and high currents. For example, in a bipolar type power semiconductor switching device in order to achieve significant conductivity modulation and reduce the drift-region resistance, high-level injection of minority carriers is typical. If the semiconductor contains a high density of crystal defects, as is the case with WBG semiconductors, minority carrier recombination phenomenon can be adversely affected. For example, it has been shown more than a decade ago [3, 4] that basal plane dislocations (BPDs) present in SiC are excited by the energy released from minority carrier recombination process; the result is excess BPD generation and its glide within the semiconductor material that leads to an increase in the drift-region resistance and thermal run-away in a forward biased bipolar junction diode The reported experimental data for high-voltage SiC semiconductor strongly suggests that material defects have profound impact on its characteristics under extreme environments. Since GaN semiconductor has even higher density of material defects, this problem is further exacerbated especially in thick epitaxial GaN layers which are required for power switches beyond 5kV. The integration of the pillar junction scheme with the trench-gate GaN MOSFET processes developed at the University of Maryland will be reported. The thick pillar junction epitaxial layers have been grown by a commercial vendor, using a windowed GaN growth process and/or selective deep etching, followed by GaN regrowth to fabricate columns with opposite carrier polarities. The doping density of the n--pillars under the gate has been specified with background carrier concentration n ≤ 1x1016 cm-3, while the p-pillars will have a higher doping density (p ≥ 1x1018 cm-3) to maximize depletion in the n--pillar. The p-body and n+-source layers are grown by subsequent epitaxial growth across the whole structure. Our current research into optimized trench gate fabrication and gate dielectric processing has been used to fabricate gate trenches into the structure. These devices can be compared to traditional trench MOSFETs with extremely thick blocking layers of comparable thickness to the pillar junction layer in order to determine the role of defects in thick GaN epi layers in terms of limiting device performance and reliability.

Optimization of Doping Profiles in Insulated-Gate Bipolar-Transistors Using a Large Scale Optimization Technique

There is much interest on the numerical and practical optimization of the doping profiles in semiconductor devices. This interest is mostly driven by the power semiconductor industry, which is in continuous search for higher breakdown voltage semiconductor switches that have lower on-state resistance, and high current handling capacity and switching speeds. Among the existing power semiconductor devices, insulated-gate bipolar-transistors (IGBTs) are becoming more and more attractive because of their high blocking voltage capabilities and on-state current. Although these devices suffer from a relatively lower switching speed compared to current state-of-the-art metal-oxide-semiconductor field-effect-transistors, IGBTs have already become the preferred switching devices in many power applications, such as induction heating applications, traction motors, etc. [1]. In this work we present numerical finite element optimization results for a realistic 70 mm-wide punch-through IGBT structure. The optimization focusses on the two-dimensional doping distribution of the gate, emitter and collector junctions, and of the drift and buffer layers in order to increase the breakdown voltage of the IGBT. The optimization method is based on an adjoint space technique that our group has recently developed for the design of nanoscale semiconductor devices, and which is adjusted here to compute the doping sensitivity functions of the breakdown voltage and on-state resistance in IGBTs [2-4]. These doping sensitivity functions show how sensitive the breakdown voltage and on-state resistance are when we add one additional acceptor or donor impurity at a particular location inside the semiconductor. Since the doping sensitivity functions provide information about the gradient of the breakdown voltage and on-state resistance with respect to the doping concentration they are instrumental for the numerical and practical optimization of IGBTs. As we will show at the conference, we are able to increase the breakdown voltage from approximately 300 V to over 700 V without deteriorating the on-state resistance of the transistor. In the full presentation we will describe how the adjoint method can be used to calculate the doping sensitivity functions of the breakdown voltage, on-state current and voltage, and on-state resistance. We will also present details about the numerical implementation of the optimization method, which is based on a modified gradient optimization appropriate for semiconductor devices. Note that most traditional optimization approaches such as the steepest descends method, the Broyden–Fletcher–Goldfarb–Shanno algorithm, or similar algorithms fail because of the doping concentration varies over many orders of magnitude, which vary can from region to region inside the same device.