Low Interface Research Articles

Independent Control of Electrical and Thermal Properties of Polymer Composites for Low Thermal Resistance Interface Materials

Electrically insulating thermal interface materials (TIMs) are desired for certain applications to avoid electrical current leakage. However, it is more challenging to achieve high thermal conductivity (κ) due to the noncoalescing nature of ceramic particles. Herein, the independent control of electrical and thermal conductivity of TIMs is reported, with the aid of low‐temperature coalescing silver nanoparticles (AgNPs), enhancing κ, and decreasing total thermal resistance (Rt) while retaining electrical insulation. The leakage‐free functionalized phase‐change material (OP) is employed as a matrix. The interaction between aluminum nitride (AlN) particles and OP induces the highest surface energy and intrinsic adhesion energy, compared with other ceramic particles, resulting in the lowest elastic modulus and Rt. The κ (1.7 W m−1 K−1) and Rt (80.1 mm2 K W−1) of the OP‐AlN are further improved by the AgNP decoration (OP‐AlN/Ag). The AlN particles are coalesced by the exquisitely functionalized AgNPs (3 vol%), suppressing electrical conductivity (<10−9 S cm−1). The κ is increased by 58% (2.7 W m−1 K−1) and Rt is decreased by 44% (45.0 mm2 K W−1). The independent electrical/thermal pathway control may prove useful for electrically insulating but thermally highly conducting TIMs.

Performance Comparison of Al2O3 Gate Dielectric Grown on 4H-SiC Substrates via Thermal and Plasma-Enhanced Atomic Layer Deposition Methods

Abstract This study systematically compared the material and electrical properties of Al2O3 films deposited on n-type 4H-SiC substrates using thermal and plasma-enhanced atomic layer deposition (ALD), referred to as PE-Al2O3 and T-Al2O3, respectively. Atomic force microscopy data indicates that the roughness of Al2O3 deposited on SiC substrates by both ALD procedures is low. X-ray photoelectron spectroscopy analysis suggests that the proportion of hydroxides on T-Al2O3 surfaces is greater than that on PE-Al2O3. Based on O 1s energy loss spectra and fitting of absorption spectra, the bandgap of Al2O3 films ranges from 6.1 to 6.2 eV, with PE-Al2O3 exhibiting a slightly higher bandgap. As for C-V data analysis of MOS capacitors, PE-Al2O3/SiC possesses a lower interface defect density and border traps in oxide layer than T-Al2O3/SiC. Further I-V testing demonstrates that the breakdown field of PE-Al2O3 is 8.7 MV/cm, with leakage current maintained at the order of 10-8 A/cm2. In contrast, T-Al2O3 displays a breakdown field of 7.2 MV/cm and a significant “soft” breakdown. The effective barrier height of PE-Al₂O₃/SiC is determined to be 1.10 eV based on Fowler-Nordheim tunneling mechanism fitting, which is greater than 0.952 eV for T-Al2O3. These results confirm the advantages of using the PEALD method.

Ultrathin Rare-Earth Oxyhalides as High-κ van der Waals Layered Dielectrics.

Van der Waals (vdW) dielectrics are extensively employed to enhance the performance of 2D electronic devices. However, current vdW dielectric materials still encounter challenges such as low dielectric constant (κ) and difficulties in synthesizing high-quality single crystals. 2D rare-earth oxyhalides (REOXs) with exceptional electrical properties present an opportunity for the exploration of novel high-κ dielectrics. In this study, for the first time, the synthesis of a series of van der Waals layered gadolinium oxyhalides with thicknesses down to monolayer through a space-confined vdW epitaxy approach and demonstrating their application as a single-crystalline gate dielectric is reported. It exhibits a remarkable relative dielectric constant exceeding 17 and an impressive breakdown field strength of 13.5MVcm-1. The 2D transistors directly gated by the REOXs layer exhibit enhanced electron mobility and a low interface trap density. An ultrahigh on/off current ratio of 109 and a near-Boltzmann-limit subthreshold swing is achieved. The superior dielectric properties, combined with the universality and scalability of the production method (e.g., millimeter-scale films are achieved), demonstrate that 2D REOXs can serve as promising gate dielectrics for 2D electronics, thereby expanding the study of high-κ vdW materials and potentially providing new opportunities for the development of low-power electronic devices.

Low interface state density and large capacitive memory window using RF sputtered NiO nanoparticles decorated MgZnO thin film

NiO nanoparticles (NPs) synthesized using glancing angle deposition (GLAD) technique over MgZnO thin film was used to design a novel memory device. The NiO NPs with average diameter ~ 9.5 nm was uniformly distributed over the MgZnO thin film surface. The MgZnO thin film/NiO NPs memory device when measured for the C-V hysteresis characteristics at varying sweep voltage demonstrated a charge trapping and de-trapping mechanism. Moreover, the device exhibited low interface states density (Dit) (1.45 × 1010 eV− 1 cm− 2) at 1 MHz and large capacitive memory of ~ 6 V at ± 7 V. The large memory window was attributed to the better interface quality between MgZnO thin film and NiO NPs. Additionally, the device also exhibited good endurance over 1000 programme/erase cycles and longer time charge retention up to 2 × 104 s. The improved performance of device and more charge accumulation capacity was primarily due to the large effective area and quantum confinement effect owing to NiO NPs. Further, on performing a resistive switching analysis, the device could show a good on-off ratio (RHRS/RLRS) of 1.24 × 102. Therefore, the proposed device structure can be a good option for future memory applications.

Favorable Contact with Low Interfacial Resistance for n-Type TiCoSb-Based Thermoelectric Devices.

In the past decade, significant efforts have been made to develop efficient half-Heusler (HH) based thermoelectric (TE) materials. However, their practical applications remain limited due to various challenges occurring during the fabrication of TE devices, particularly the development of stable contacts with low interfacial resistance. In this study, we have made an effort to explore a stable contact material with low interfacial resistance for an n-type TiCoSb-based TE material, specifically Ti0.85Nb0.15CoSb0.96Bi0.04 as a proof of concept, using a straightforward facile synthesis route of spark plasma sintering. We tested many metals with compatible coefficients of thermal expansion to TiCoSb, like Fe and Co. Still, we failed to form proper atomic bonds with the TE material. In contrast, Ti metal bonded correctly but showed very high electrical contact resistance (∼300 mΩ at one side), reducing performance due to Ti diffusion and a high potential barrier at the interface. This issue was addressed by highly doped semiconductor (HDS) contact Ti0.7Nb0.3CoSb, which matched the TE material in terms of atomic bonding, crystal structure, and stability. The leg with the HDS contact demonstrated superior electronic transport performance and low interface resistance (∼15 mΩ at one side), achieving a maximum output power of 30.7 mW at ΔT = 451 K due to the sharp interface with a low barrier height. These findings suggest that using HDS material as a contact with the same HH TE material would be an effective way to develop a TE device with low interface resistance and high thermal stability.

Capacitorless Dynamic Random Access Memory with 2D Transistors by One-Step Transfer of van der Waals Dielectrics and Electrodes.

Dynamic random access memory (DRAM) has been a cornerstone of modern computing, but it faces challenges as technology scales down, particularly due to the mismatch between reduced storage capacitance and increasing OFF current. The capacitorless 2T0C DRAM architecture is recognized for its potential to offer superior area efficiency and reduced refresh rate requirements by eliminating the traditional capacitor. The exploration of two-dimensional (2D) materials further enhances scaling possibilities, though the absence of dangling bonds complicates the deposition of high-quality dielectrics. Here, we present a hexagonal boron nitride (h-BN)-assisted process for one-step transfer of van der Waals dielectrics and electrodes in 2D transistors with clean interfaces. The transferred aluminum oxide (Al2O3), formed by oxidizing aluminum (Al), exhibits exceptional flatness and uniformity, preserving the intrinsic properties of the 2D semiconductors without introducing doping effects. The MoS2 transistor exhibits an extremely low interface trap density of about 3 × 1011 cm-2 eV-1 and a leakage current density down to 10-7 A cm-2, which enables effective charge storage at the gate stack. This method allows for the simultaneous fabrication of two damage-free MoS2 transistors to form a capacitorless 2T0C DRAM cell, enhancing compatibility with 2D materials. The ultralow leakage current optimizes data retention and power efficiency. The fabricated 2T0C DRAM exhibits a rapid write speed of 20 ns, long data retention exceeding 1,000 s, and low energy consumption of approximately 0.2 fJ per write operation. Additionally, it demonstrates 3-bit storage capability and exceptional stability across numerous write/erase cycles.

Two-dimensional Green’s function for an isotropic equal-thickness double-layer structure

According to Green’s function for a half-infinite plane subjected to a concentrated force, a two-dimensional Green’s function is derived for an isotropic double-layer structure of equal thickness under a concentrated force applied above the surface. This derivation was based on the mirroring image method and Dirichlet’s principle of singularity. Initially, the characteristics of the equal-thickness double-layer structure were examined, leading to the formulation of the upper and lower surface and interface conditions of the computational structure. Subsequently, four series of harmonic functions were generated from ten harmonic functions using the general solutions to two harmonic functions. By substituting these four series functions into a two-dimensional general solution, eight recursive equations were derived. The equations were expressed through eight harmonic functions, which could be solved using the upper and lower surface conditions and interface connection conditions. The harmonic function under any force can be determined through Green’s function for an isotropic half-infinite plane structure, allowing for the computation of the displacement and stress fields of the isotropic double-layer structure with equal thickness. Finally, numerical examples were used to compare the interface calculation results of this study with the finite element method numerical results, demonstrating the validity of the algorithm. This method is computationally simple and converges quickly. Utilizing the principle of superposition, the stress fields and displacements of an isotropic finite element method equal-thickness double-layer structure can be solved for any directional force acting on the surface, providing a robust foundation for the engineering design and analysis of such problems.

Impact of Deposition Temperature on Structural and Electrical Properties of Sputtered AlN/ Si (111) for CMOS compatible MEMS

Aluminium nitride (AlN) thin films are grown by reactive sputtering on Silicon (Si) with (111) orientation at low temperature (< 450 °C) for piezoelectric-based micro-electromechanical systems (MEMS). The grown AlN thin films were polycrystalline wurtzite hexagonal structure with a high texture coefficient for the (002) plane of orientation. The leakage current density by the current-voltage (I-V) measurement was found to be as low as 1.6 ×10-6Acm−2 in the grown films. The trapped charges are crucial in controlling these electrical characteristics, and low interface trap density (6.72 ×1010cm−2 eV) was observed for the sputtered AlN grown at a substrate temperature of 300 °C. This study on the structural and electrical properties of AlN/Si (111) at low substrate temperature is compatible with the complementary metal oxide semiconductor (CMOS) process for constructing piezoelectric-based MEMS devices for various applications.

Unlocking the Performance of Next-generation Non-volatile Capacitive Memory Devices with Ti-doped ZnO Nano Wires via Pulsed Laser Deposition

This paper investigates the impact of titanium (Ti) doping on zinc oxide (ZnO) nano wires (NWs) in non-volatile capacitive memory devices (NVCMDs) through fabrication and characterizations. ZnO NWs were fabricated using pulsed laser deposition (PLD), while Ti thin film (TF) was deposited via electron beam evaporation (e-beam). Field emission gun scanning electron microscopy (FEGSEM) confirmed the formation of ZnO NWs and Ti-doped ZnO NWs (Ti:ZnO NWs) on an n-type silicon (Si) substrates, with elemental compositions determined by energy dispersive X-ray spectroscopy (EDX). Structural characterization was conducted on the samples using high-resolution X-ray diffraction (HRXRD). Gold (Au) interdigitated electrodes (IDE) were employed to fabricate two distinct devices: Au IDE/ZnO NWs and Au IDE/Ti:ZnO NWs. Comparative analysis revealed that the Au IDE/Ti:ZnO NWs device exhibited a lower frequency dispersion fd value (0.025×109 F) compared to Au IDE/ZnO NWs device (0.029×109 F), indicating enhanced signal propagation due to Ti doping. The Au IDE/Ti:ZnO NWs device also demonstrated a high free charge carrier donor concentration ND value of 2.02×1012 /cm3, a significant trap concentration Nt value of 4.44×1011 /cm3 at an 8MHz frequency response. Additionally, it exhibited lower tangent loss (tan(δ)) value of 7430, maximum conductance Gmmax value of 13.40 mS, lower interface trap state density (ITSD) value of 2.05×1014 eV1 cm2, a maximum memory window (∆VMW) of 6.9V at ±15V, improved endurance, and superior data retention, making the Au IDE/Ti:ZnO NWs device a promising candidate for next-generation NVCMDs applications.

Heterostructured Al2O3@BNNS/epoxy‐POSS/epoxy composites with excellent thermal conductivity, dielectric, and thermal properties

AbstractHigh thermal conductivity (λ) composite with excellent dielectric, mechanical, and thermal properties are critical to the reliability and safety of electrical devices. However, the excessive addition of thermal conductive fillers may lead to severe performance degradation. Heterogeneous structured alumina‐hexagonal boron nitride nanosheets (Al2O3@BNNS) fillers were prepared by electrostatic self‐assembly method. Owing to synergistic effect of spherical Al2O3 and sheet BN, and much low interface thermal resistance, λ of the epoxy resin with 20 wt% Al2O3@BNNS2 is raised to 0.84 W·m−1·K−1, 86.67% higher than that of Al2O3/BN/EP composite. Furthermore, epoxy‐based polyhedral oligomeric silsesquioxane (EP‐POSS) was incorporated to further optimize dielectric property of the composite. The λ of the composite is slightly decreased, but the dielectric constant and dielectric loss are reduced to 2.954 and 0.01058, respectively, due to the unique cage structure of EP‐POSS and excellent compatibility of EP‐POSS with the matrix. The composite also exhibits favorable mechanical properties with an impact strength of 86.2 MPa and a bending strength of 7.81 kJ·m−2, as well as outstanding thermal stability, suggesting its promising prospects for advanced electronic devices.Highlights fAl2O3 and fBNNS electrostatic self‐assemble into heterostructured fillers. The λ of Al2O3@BNNS2/EP composite is much higher than the others. The cage‐like EP‐POSS is used to improve dielectric properties of the epoxy resin. The ε and tanδ of composites at 1 MHz are only 2.954 and 0.01058, respectively.

Dispersion and Tribological Behaviors of Modified Functionalized Surfaces of Single and Hybrid Nanoparticles in Water-Based Lubrication

This study investigated the dispersion and tribological effetcs of modifying surface functionalization on single (GO, Al2O3, MgO, SiC) and hybrid (SiC/MgO, Al2O3/MgO) nanoparticles in water-based lubricant (WBL) formulations. Polyvinylpyrrolidone (PVP) and glycerol were utilized to further enhance dispersion and viscosity. The experimental findings revealed that incorporating modified nanoparticles surfaces in WBLs improved hydrophilicity and dispersion by introducing additional oxygen functional groups. This effectively reduced direct metal-to-metal contact, resulting in lower interface temperatures and enhanced tribological performance. Hybrid Al2O3/MgO nanoparticles exhibited a significant 76.69 percent enhancement in tribological performance in wear mechanisms, synergistically filling microcracks to improve lubricant film formation, bearing, and mending effects. Using a single nanoparticle was found to be insufficient for achieving enhanced tribological effects. All nanoparticles improved bearing effects, except for GO, which promoted a shearing effect. High-hardness nanoparticles such as SiC and Al2O3 demonstrated an additional polishing effect.

Nanosecond laser annealing: Impact on superconducting silicon on insulator monocrystalline epilayers

We present superconducting monocrystalline silicon-on-insulator thin 33 nm epilayers. They are obtained by nanosecond laser annealing under ultra-high vacuum on 300 mm wafers heavily pre-implanted with boron (2.5 × 1016 at./cm2, 3 keV). Superconductivity is discussed in relation to the structural, electrical, and material properties, a step toward the integration of ultra-doped superconducting Si at large scale. In particular, we highlight the effect of the nanosecond laser annealing energy and the impact of multiple laser anneals. Increasing the energy leads to a linear increase in the layer thickness and to the increase in the superconducting critical temperature Tc from zero (&amp;lt; 35 mK) to 0.5 K. This value is comparable with superconducting Si layers realized by gas immersion laser doping, where dopants are incorporated without introducing the deep defects associated with implantation. Superconductivity only appears when the annealed depth exceeds the initial amorphous layer induced by the boron implantation. Multiple subsequent anneals result in a more homogeneous doping with reduced amount of structural defects and increased conductivity. The quantitative analysis of Tc concludes on a superconducting–non-superconducting bilayer with an extremely low resistance interface. This highlights the possibility to efficiently couple superconducting Si to Si channels.

Thick β-Ga2O3 homoepitaxial films grown on ([formula omitted]01) substrate by mist-CVD

Thick β-Ga2O3 homoepitaxial films have been grown on (2¯01) commercial substrates by mist-CVD with gallium acetylacetonate precursor for the first time. The growth rate of about 2 μm/h has been reached, which is unavailable for any other known epitaxial technique. The layer is characterized by the constant thickness and reasonable structure quality due to low stressed interface.

Hollow amorphous N-doped TiO2 microspheres with uniform shell thickness and high carrier separation efficiency for photocatalytic of high-concentration Cr(VI)

Due to the low quantum efficiency, pure N-doped TiO2 (NTO) is still ineffective for catalyzing high concentrations of pollutants. In this study, a novel hollow amorphous NTO photocatalyst (AH-NTO) was synthesized by ultrasonic-assisted hydrothermal method and applied to photocatalysis of high-concentration chromium-containing wastewater. The hollow structure was constructed using a three-dimensional Fe3O4 template, and the shell layer thickness changed regularly compared to the stirring method, suggesting that ultrasound contributes to the formation of a uniform shell. Meanwhile, the low crystallization kinetics induced by the ultrasound-assisted low-temperature hydrolysis process enhance the generation and stability of amorphous NTO. Characterization of the system demonstrated that the hollow amorphous structure improved visible-light utilization efficiency (∼70 % light transmittance) and specific surface area (182.95 m2 g−1). Furthermore, the optimal photocatalyst exhibited a high photogenerated carrier signal (0.231 μA cm−2), low interface resistance (374.8 Ω), and a strong oxygen vacancy signal (∼0.38 a.u.), which provides favorable conditions for the separation and transfer of photogenerated carriers. Based on these properties, the photocatalyst effectively treated wastewater containing 0.274 g L−1 of Cr(VI). The removal efficiency decreased by only 0.18 % over five consecutive cycles, demonstrating excellent cycle stability and activity. Therefore, this work provides a practical case for treating high-concentration pollutants.

Low Interface Trap Density 4H-SiC MIS Structure With SiO₂ Grown by Sub- 1000 °C Intermittent Spray Hydrated Oxidation (ISHO) for UV Sensor Applications

Low Interface Trap Density 4H-SiC MIS Structure With SiO₂ Grown by Sub- 1000 °C Intermittent Spray Hydrated Oxidation (ISHO) for UV Sensor Applications

Enhanced Electrical Performance of InAs Nanowire Field-Effect Transistors Based on the Y2O3 Isolation Layer.

Nanowire (NW) field-effect transistors (FETs) have great potential in next-generation integrated circuits. InAs NWs are suitable for N-type transistors because of their excellent electrical properties. However, unlike the Si/SiO2 system, the loose and defective native oxide of InAs is unable to passivate the channel surface and serve as an efficient isolation layer (IL) in the gate stack. Here, we, for the first time, demonstrate that using a stable dielectric Y2O3 to replace the native oxide IL can effectively passivate the NW surface, isolate the channel surface from high-k HfO2, and improve the electrical properties of InAs NW FETs significantly. First, top-gate devices with Y2O3 IL outperform the devices with native oxide or chemically generated oxide of InAs as the IL, exhibiting a small subthreshold swing (SS) of 77 mV/dec, a large on-off ratio, a high field-effect mobility (μFE) of 1845 cm2/V·s, and an extremely low interface trap density (Dit) of 9.1 × 1011 eV-1 cm-2. Double-gate FETs with Y2O3 IL also show excellent gate control (drain-induced barrier lowering (DIBL) down to 35 mV/V) and a high μFE of 2711 cm2/V·s (the highest in the multigate structure). In addition, InAs NW FETs with Y2O3 IL show greater stability after long-term air exposure than those with native oxide IL, demonstrating retained on-off ratio, DIBL, transconductance, and even smaller SS (from 89 to 77 mV/dec). Finally, the results of low-temperature measurement suggest that Y2O3 IL can effectively improve interface qualities. Our results indicate that Y2O3/HfO2 InAs NW FETs have great potential in digital units of integrated circuits for future nodes. Our strategy for improving the interface between InAs NW and the dielectric layer is also valuable for other III-V NW devices.

2,2-Dimethylvinylboronic acid as an effective solid electrolyte interface formation additive for high performance sodium ion batteries

The main challenges brought by the unstable solid electrolyte interface (SEI) film seriously hinder the practical application of sodium ion batteries (SIBs). Herein, 2,2-dimethylvinylboronic acid (DEBA) is used as a film-forming electrolyte additive to improve the stability of the interface between the hard carbon (HC) and electrolyte for SIBs, naming the resulting electrode HCD-DEBA. DEBA is preferentially decomposed before the electrolyte and involved in forming SEI. Besides, in the cycling process, the C=C bonds in DEBA undergo the in-situ polymerization to construct the polymer skeleton of the SEI, inducing forming a thinner solid electrolyte interface layer with lower interface impedance, thus enhancing cycling stability. The optimized HCD-2%DEBA exhibits a first-cycle discharge specific capacity of 332.5 mAh g−1 at 0.1 C, while the HCD is 329.6 mAh g−1. HCD-2% DEBA was able to cycle 5000 times at a high rate of 5 C with capacities ranging from 195.7 mAh g−1 to 110.4 mAh g−1, however, the one without DEBA died after about 2000 cycles with an initial discharge capacity of 83.6 mAh g−1. This work provides a simple strategy for improving the cycle capacity of hard carbon half-cells and constructing the solid electrolyte interphase.

Construction of grass carp myofibrillar protein/rutin Pickering emulsion gel by one-step method and multi-scale analysis

Polyphenols can be used as an amending agent for protein emulsions. The effect of rutin addition on grass carp myofibrillar (GMP) stabilized Pickering emulsions was investigated. With the increase of rutin concentration, the particle size of GMP/rutin decreased (∼3760 nm to ∼279 nm), and the contact angle increased (53.88° to 73.93°) with higher α-helix and random coil ratio in protein secondary structure. The surface activity of protein-rutin was improved reflected by the lower oil-water interface tension. With the increase of rutin, the viscoelasticity and gel strength of the emulsion were significantly increased (P < 0.05). The emulsion droplets showed more densely packed structure with GMP/rutin particles surrounding the droplets. The presence of rutin improved the centrafuge and oxidation stability of the emulsion. Herein, GMP/rutin can be used as a food-grade emulsifier/stabilizer for Pickering emulsions with enhanced emulsifying properties and provides basis for the high value-added utilization of GMP.

(Invited) Interface Control Process of Rare-Earth Oxides on Si for Gate Dielectric Application

High-k gate dielectrics are indispensable to overcome the shot-channel effect in scaled CMOS devices [1]. Besides the enhanced electrostatic control of the gate electrode, high-k/Si interface properties, including interface state density, fixed charges, dipoles, carrier mobility, reliability, and so on, need to meet the requirement levels. Rare earth oxides have been intensively studied for gate dielectric applications as these oxides react with Si to form a silicate layer, whereas, for the HfO2 case, a SiO2-based low-k interface layer is formed. One of the issues for rare earth oxide gate dielectrics is controlling the reaction amount while obtaining a good interface property. In this presentation, the interface reaction of rare-earth oxides and Si is modeled and controlled by the thermal treatment process. Furthermore, the influence of the metal gate electrode on the interface is assessed. A la-silicate interface layer is formed between the La2O3 film and Si interface. Although the La atom content in the reactively formed silicate layer generally depends on the annealing environment, a silicate/Si interface can be easily formed, which is advantageous for gate dielectric scaling. However, even under the same process, the La atom content in the silicate increases with the thinning of the initial La2O3 thickness, and the interface state density, flat-band voltage, and mobility degrade [2]. The reaction between La2O3 and Si can be modeled by oxygen atom supply from the environment, and the influence of the metal gate can explain the degradation of electrical properties. A La-rich silicate can be formed with nice interface properties by controlling the supplied oxygen atoms by selecting a proper metal gate stack [3]. The crystal grain size in the metal gate also affects the interface state density. A low interface state density can be obtained by adopting a metal gate material with nano-sized grains [4].In conclusion, an interface control process of La2O3 film on Si is presented by limiting the oxygen atom supply during the interface reaction. La-rich silicate, a high-k film, can be obtained by adopting a proper stacked gate structure. Also, nano-sized grains in the metal electrodes can exhibit a decent interface property.[1] J. Robertson, et al., Materials Science and Engineering R, 88, 1 (2015).[2] K. Kakushima, et al., Solid-State Electron., 54, 715 (2010).[3] T. Kawanago, et al., IEEE Trans. on ED, 59, 269 (2011).[4] K. Tuokedaerhan, et al., Appl. Phys. Lett., 104, 021601 (2014).

(Invited) Silicon Carbide Technology Scaling: Challenges and Opportunities across the Value Chain

Silicon Carbide (SiC) technology has emerged as a promising solution to address the growing demand for high-performance power electronics in various applications, ranging from automotive to renewable energy systems. As the industry continues to push the boundaries of SiC technology, scaling opportunities and challenges arise across the entire value chain, from material to device fabrication and new package architectures. In addition, it should be noted that scientific understanding, especially in the areas of defect behaviour in the SiC epitaxy layer, threshold voltage instability, interface trap density, and integrity of the gate insulator, would be increasingly important and necessary for the further development of SiC power devices. To address the economics, and mass produce ultra-high-power electronics devices with improved performance and reliability, we partnered with ecosystem players across the value chain from substrate to power module packaging and set up a 200mm SiC specialty open innovation process line.This talk will provide an overview of the key challenges and opportunities associated with SiC technology. We will discuss the high grow rate (≥50µm/hr) SiC epitaxy process and share methodologies to achieve high-quality epitaxy layer with good doping control (≤10%), tight thickness uniformity (≤3%), low surface roughness (≤3Å) and low crystal defect densities (≤0.4 cm-2) on 200mm 4H-SiC substrate. Moving on to the metal oxide semiconductor (MOS) device interface engineering, we will discuss strategies for achieving low interface trap densities (~1011eV-1 cm-2) and improved threshold voltage instability. Beyond device fabrication, we will highlight the importance of the power module packaging technique in realizing the full potential of SiC technology. This includes the double-side liquid cooling system and the power dissipation capability with different designs and material options for the proposed 6-in-1 power module.Overall, by addressing these challenges collaboratively, we can accelerate the adoption of SiC technology and unlock its full potential to drive power semiconductor technology and beyond. Figure 1