Lower Wafer Research Articles

High-Precision Wafer Bonding Alignment Mark Using Moiré Fringes and Digital Grating.

This paper investigates a moiré-based mark for high-precision wafer bonding alignment. During alignment, the mark is combined with digital grating, which has the benefits of high precision and small size. A digital grating is superimposed on the mark to generate moiré fringes. By performing a phase calculation on the moiré fringe images corresponding to the upper and lower wafers, the relative offset of the upper and lower wafers can be accurately calculated. These moiré fringes are exceptionally stable, thereby enhancing the alignment stability. In this study, through practical experiments, we tested the rationality and practicability of the mark.

Material Design Advancement Create Multifunctional Materials for Single-Layer Bonding and Debonding

Multifunctional materials are a relatively new topic in the semiconductor industry for wafer-level packaging (WLP). With the increase in processing steps and the emergence of more advanced technologies, the use of multifunctional materials will become a more integral part in the future of temporary bonding and debonding (TB/DB) as well as other advanced packaging applications. One approach to multifunctional material design incorporates adhesive and laser release attributes in one material layer. Although this is similar to a thermal release material, it has greater thermal capabilities due to its ability to be cured and undergo laser debond. Many advantages may be obtained by combining a curable adhesive and laser release layer into one material. One of the greatest advantages is the reduction in overall processing time and steps required to bond wafer pairs as well as the reduction of chemical waste, due to the use of one material compared to two or more materials which significantly reduces the cost of ownership. Curable adhesive single layer systems offer access to higher temperatures with less material flow from the curable layer, strong adhesion for high stress applications where wafers can delaminate or spontaneously debond when using multilayer mechanically debonding systems such as Fan-Out Wafer Level Packaging (FOWLP), and offer lower wafer stress and warpage due to fewer material interfaces within the bonded wafer pairs causing less potential mismatch of materials coefficient of thermal expansion(CTE). Some challenges with this concept stem from the concern of the cleanability of a curable layer and potential laser damage to the device. In order to wet clean a curable layer, which is usually very solvent resistant due to the crosslinked nature, requires harsh solvent based solutions (that may contain either strong acid or base, require long cleaning time, and high temperature). This study will address all of the aforementioned challenges and includes the developmental advancements in material designs that resulted in the creation of new multifunctional materials. These multifunctional materials have been designed to be thermally curable, prevent material reflow of the bonding layer at higher temperatures, while still remaining wet cleanable without the use of harsh chemicals and long times. As with any material that utilize laser release methods there are concerns about device damage from laser energy penetrating to the device but multifunctional materials address this in two ways: they offer high absorbance of the laser energy at all commercially available laser tool wavelengths and they can be utilized as a thicker film as they act as the bonding layer as well. By overcoming their challenges, they will minimize the cost of ownership while driving advancement in future materials and processing.

Bonding of SiO2 and SiO2 at Room Temperature Using Si Ultrathin Film

In three-dimensional integration technology, the bonding of metal electrode and insulator hybrid interface is very important technique. The hybrid interface serves as both an electrical connection and mechanical bond. However, the bonding of these hybrid interfaces is a challenging issue. Since the conventional bonding process requires high-temperature annealing, there exist various problems such as thermal damage, low throughput, and low alignment accuracy. As the surface activated bonding (SAB) is a bonding method carried out at room or low temperatures [1], the bonding method is expected to solve these problems. By the SAB method, direct bonding metal materials such as Cu or Al is easy. However, it is very difficult to directly bond insulator materials such as SiO2 or SiN [2], because these surfaces are rendered inactive immediately after being activated. We have reported on the bonding technique at room temperature using only Si ultrathin films for insulator materials, and we have shown that high bonding strength is achieved [3]. The surface of electrode is also covered with Si film by this bonding method. Thus, it is very important to reveal the influence of this Si film thickness on the SiO2/SiO2 bonding. In this report, we have investigated the relationship between the SiO2/SiO2bonding strength and the thickness of Si ultrathin film. Figure 1 shows a schematic illustration of the bonding apparatus (Mitsubishi Heavy Industries, Ltd., MWB-08AX) used in this experiment. Surface activation is carried out by an Ar fast atom beam (FAB). In the normal SAB process, the upper and lower wafers are irradiated with the Ar-FAB at the same time. The bonding procedure which we propose for hybrid bonding is as follows. The one of bonding wafers is held by the electric static chuck (ESC), and Si blanket wafer is placed on the lower side as the sputtering target. First, only the lower wafer is irradiated with FAB1 (first irradiation) after activating electrode surface of the upper wafer. The blanket Si wafer is then exchanged with the other bonding wafer. Only the upper wafer is irradiated with FAB2 (second irradiation) after activating electrode surface of the lower wafer, and the Si film surface on the upper wafer is also etched by FAB2. A Si thin film is then deposited on the lower wafer surface. The upper wafer and the lower wafer are optically aligned and then bonded with high load.Figure 2 shows the relationship between the surface energy and the Si ultrathin film thickness for the bonding of Si blanket wafers (8 in) with a thermal oxide. Applied voltage and current of Ar beam source operated in these experiments were about 1.8 kV and 100 mA, respectively. The background vacuum pressure is about 2×10-6Pa. The surface energy of wafers was about 1 J/m2 for thicker than about 3 nm. A cross-sectional TEM image of SiO2/SiO2bonding is shown in Fig. 3. The bonded wafers were treated with a FAB1 irradiation time of 5 min and a FAB2 irradiation time of 1 min. No micro voids were observed, and Si intermediate layer, of which the thickness is about 3nm, was seen at the bonding interface.In conclusion, we showed that high bonding strength was achieved in SiO2/SiO2 bonding with the Si film thickness of about 3 nm by this bonding method. Reference:[1] H. Takagi, K. Kikuchi, R. Maeda, T. R. Chung, and T. Suga, Appl. Phys. Lett. 68, 2222 (1996).[2] H. Takagi, R. Maeda, T. R. Chung, and T. Suga, Sensors and Actuators, A 70, 164 (1998).[3] J. Utsumi, K. Ide, and Y. Ichiyanagi, Jpn. J. Appl. Phys., 55, 026503 (2016). Figure 1

A New Isolation Technology for Automotive Power-Integrated-Circuit Applications

In this paper, a new bulk silicon isolation structure with wafer-thick trenches is proposed for automotive (42 V) power-integrated-circuit applications. This technology provides the advantages of complete isolation with lower wafer cost and higher thermal-dissipation capability as compared with the silicon-on-insulator technology. Experimental results show that the new isolation structure can provide complete electrical isolation and with a 13% reduction in thermal resistance.

Influence of a Retaining Ring on Strain and Stress in the Chemical Mechanical Polishing Process

In this article, a two-dimensional axisymmetric quasi-static finite element wafer scale model for chemical mechanical polishing (CMP) process involved in the wafer carrier, the carrier film, the wafer, the pad, and the retaining ring was developed to investigate the effect of a retaining ring surrounding the wafer carrier to the strain, stress, and nonuniformity of the wafer surface for the purpose of improving edge exclusion of wafer and preventing the wafer sliding from the carrier while grinding. Considering the same revolutions of the wafer and the pad and the axisymmetric distributed force forms of the wafer carrier and the retaining ring, and applying the principle of minimum potential energy, a two-dimensional axisymmetric quasi-static finite element model for CMP process was established. Following the developed model, the effects of the retaining ring on the strain components, the stress components, the von Mises stress, and the wafer's nonuniformity were investigated. The findings indicated that a retaining ring installed in the conventional CMP mechanism could reduce the variation of the von Mises stress distribution to reach the lower wafer's nonuniformity effectively, improve the over-grinding phenomenon and prevent the wafer sliding from the carrier while grinding.

Wafer Level Three-Dimensional Integration Technology for MEMS.

Presumably the 21st century will see an advanced information society in which multimedia equipment is in common use. One of the basic technologies that support MEMS (Micro Electro Mechanical Systems), a new idea called “electronic systems integration”for practical application of an integrated block in which many different elements including not only electronic circuits but also sensors and actuators are combined, using Si wafers as basic elements. With today's MEMS, the problems of suppressing delay in signal transmission and heat generation are highlighted, and intensive investigations are being conducted on such methods as three-dimensional packaging to miniaturize low-resistance Cu trenches (Damascene) and low-permittivity layer insulation films and wires. The problem with waferlevel three-dimensional packaging is how to carry out wiring between upper and lower wafers at the time of stacking. In the past practice, stacked wafers were connected through inner bumps formed on the through-hole interconnections. However, the bumps had to be polished to make them uniform in height because they were difficult to form with a uniform height. In order to solve this problem, we developed a technology of wiring wafers to each other by the molten metal suction method after stacking them in several layers in the three-dimensional direction, i.e., we succeeded in connecting wafers without bumps. The purpose of the present paper is to introduce this technology.

Micro-opto-mechanical grating switches

This paper reports the design, fabrication, and testing of a Micro-opto-mechanical grating switch driven by electrostatic actuator for fiber-optic communication applications. It consists of two bounded silicon wafers. One input fiber with a hemispherical lens at its end and three photodetectors are mounted on the upper wafer. A movable platform with two gratings and one mirror are fabricated on the lower wafer. When the movable platform is at a certain position, the input beam can be split into three beams by the gratings. The reflectivity of the mirror is about 85% while the efficiency in the three different order is 29%, 26%, and 26%. The switching speed is about 500 μs. Details of the grating switching design, theoretical analysis, fabrication and experimental results are presented in this paper.

Measurement of Stress and Strain of Single-Crystal-Silicon Thin Film during On-Chip Tensile Test

We investigated a new measurement method of mechanical characteristics of thin films which are used as structural materials in MEMS devices. This on-chip tensile testing method is characterized by that the tensile specimen and loading mechanisms are integrated on a same silicon chip. We proved the accuracy of the stress and strain measurement by measuring Young's moduli of single-crystal silicon films having different crystallographic orientations. The measured Young's moduli showed good agreement with results from separately performed bending test and values in literature. Thus we concluded that the stress and strain measurement was correctly performed with our new method.We developed a fabrication process of testing chip that allows tensile testing of single-crystal silicon film having arbitrary crystallographic orientations. The process starts with an SOI wafer whose top layer having a certain orientation was carefully aligned against the lower wafer. With three steps of etching, we fabricated test chips of 12×12×0.4mm, containing a specimen of 14_??_21μm thick, 80μm wide, and 400μm long.