Low Turn-off Loss Research Articles

A Critical Analysis and Comparison of the Effect of Source Inductance on 3- and 4-Lead SuperJunction MOSFETs Turn-Off

This paper critically compares the turn-off performance of two package solutions, 3-lead (3L) vs. 4-lead (4L), in SuperJunction MOSFETs. It is commonly assumed that the better performance (lower switching losses) of the 4L MOSFET is obtained thanks to the decoupling of the power and driving loops. On the contrary, in this work, the experimental results, circuit models and Kirchhoff laws show that the turn-off improvement (lower turn-off losses) obtained by adopting the Kelvin source is due to the lower inductance of the driver loop of the 4L MOSFET, instead of the decoupling between the driver and power loops. In detail, an inductor is added to the gate path of the 4L MOSFET to obtain a total inductance in the driver loop equal to the 3L counterpart. The experimental results show that the 4L MOSFET presents the same drain current slew rate under this condition, although the driver and power loops are still decoupled.

Self-clamped P-shield 4H-SiC trench MOSFET for low turn-off loss and suppress switching oscillation

A novel 4H-SiC trench MOSFET with self-clamped P-region (SCP-MOS) is proposed. The breakdown voltage is boosted and switching oscillation is suppressed by introducing a lightly P-type doping concentration region (LP) and additional NCSL. P+ and NCSL form a new electric field modulation region that reduces the electric field at the bottom of the gate, resulting in a higher breakdown voltage for the device. Moreover, When VDS is small, the LP region links P-shield and P+ source region, the P-shield is clamped at a low potential, which effectively reduces the gate to drain capacitance (CGD). As VDS increases, the LP region is gradually depleted, causing the P-shield to transition into floating state, the potential in the P-shield region is raised. Consequently, the described characteristics facilitate achieving low turn-off losses and Surge voltage(VSurge). SCP-MOS has 32 % lower surge voltage compared to GP-MOS and 85 % lower turn-off loss compared to FP-MOS. Overall, SCP-MOS can obtain better EOFF-VSurge trade-off.

Simulation Study of 4H-SiC Low Turn-Off Loss and Snapback-Free Reverse-Conducting Gate Turn-Off Thyristor with N-Float Structure

In this study, a novel integrated 4H-SiC reverse-conducting gate turn-off thyristor (GTO) featuring an N-type floating (NF) structure is proposed. The proposed NF-structured 4H-SiC GTO outperforms conventional reverse-conducting GTOs in forward conduction, effectively eliminating the snapback phenomenon. This is achieved by increasing lateral resistance above the P-injector and modifying the electron current path during early turn-on. NF structures with a doping concentration of 2 × 1014 cm−3 and thicknesses exceeding 4 μm have been indicated to successfully eliminate the snapback phenomenon. Moreover, the anode-shorted structure enhances the GTO’s breakdown voltage and concurrently reduces turn-off losses by 85% at low current densities.

A Float P-Drift and Blocking Junction LIGBT With Low Turn-Off Loss and No-Snapback

A Float P-Drift and Blocking Junction LIGBT With Low Turn-Off Loss and No-Snapback

Noval carrier accumulation reverse-conducting lateral insulated gate bipolar transistor

Reverse-conducting lateral insulated gate bipolar transistor (RC-LIGBT) with freewheeling diode integrated in the body by introducing n<sup>+</sup> anode can realize the reverse conduction and optimize the turn-off characteristics of the device, which is a promising device in a power integrated circuit. In this work, a novel RC-LIGBT with electron-controlled gate (EG) and separated short-anode (SSA) is proposed and investigated by TCAD simulation, which can achieve low on-state voltage drop (<i>V</i><sub>on</sub>) and low turn-off loss (<i>E</i><sub>off</sub>) at the same time. The EG structure of p-n-n<sup>+</sup>-p (p<sup>+</sup> region/n-type silicon region/n-type barrier layer/p<sup>+</sup> region) is adopted, the gate electrode and anode electrode are connected by the EG structure. In the forward conduction state, a high-density electron accumulation layer is formed on the surface of the drift region by EG structure, which greatly reduces the <i>V</i><sub>on</sub> of the device. At the same time, the use of the SSA structure can also optimize the <i>E</i><sub>off</sub> of the device by forming an additional electron extraction channel. In addition, based on the EG structure, a low-doping p-drift can be combined with the SSA structure to simply achieve reverse-conduction and snapback-free characteristics. Furthermore, the EG structure and the SSA structure can complement each other. On the one hand, the high-density electron accumulation layer formed by EG structure compensates for the weakened conductance modulation effect caused by the SSA structure. On the other hand, the electron extraction channel of the SSA structure enables a large number of accumulated electrons to be removed quickly. The simulation results show that the proposed device has an excellent trade-off relationship between <i>V</i><sub>on</sub> and <i>E</i><sub>off</sub>, specifically, <i>V</i><sub>on</sub> is 1.16V, which is 55% lower than that of SSA LIGBT, and <i>E</i><sub>off</sub> is 0.099 mJ/cm<sup>2</sup>, which is 38.5% and 94.7% lower than that of SSA LIGBT and conventional LIGBT, respectively.

Low Turn-Off Loss Lateral Insulated Gate Bipolar Transistor With Double Deep P-Regions

Low Turn-Off Loss Lateral Insulated Gate Bipolar Transistor With Double Deep P-Regions

Simulation Study of Low Turn-Off Loss and Snapback-Free SA-IGBT with Injection-Enhanced p-Floating Layer

In this study, a shorted-anode IGBT with an injection-enhanced p-floating layer (IEPF-IGBT) under the N-buffer layer is proposed. Compared to conventional shorted-anode IGBT (SA-IGBT), the IEPF-IGBT has the structural characteristics of an injection-enhanced P-floating (IEPF) layer inserted into the N-buffer layer and the P+ collector region. The IEPF layer and P+ collector region pinch off the electron path during the turn-on period to suppress the snapback effect with a half-cell pitch of 10 μm. In addition, the IEPF layer acts as an injection-enhanced layer that influences the current injection of the holes. There is 56.3% reduction in the turn-off loss of the IEPF-IGBT at the same forward voltage drop.

Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

The influence of the recovery characteristics on the switching behavior of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with different switching speeds was investigated. A comparative analysis of the devices with different recovery characteristics revealed an increase in the turn-on loss (Eon) owing to the higher output capacitance charge (Qoss) and reverse recovery charge (Qrr) in the recovery arm. On the other hand, a higher Qoss in the recovery arm resulted in a lower turn-off loss (Eoff). In addition, an increase in Qoss and Qrr further influenced Eon and Eoff at a higher switching speed. Furthermore, a higher Qrr observed at a higher switching speed indicated a more significant impact of Qrr on Eon at a high switching speed than that of Qoss. The findings clarified in this study highlight the necessity of focusing the recovery characteristics to ensure a desirable switching loss of SiC MOSFETs.

A Snapback-Free and Low Turn-Off Loss 15 kV 4H–SiC IGBT with Multifunctional P-Floating Layer

In this paper, a 4H–SiC IGBT with a multifunctional P-floating layer (MP-IGBT) is proposed and investigated by Silvaco TCAD simulations. Compared with the conventional 4H–SiC field stop IGBT (FS-IGBT), the MP-IGBT structure features a P-floating layer structure under the N-buffer layer. The P-floating layer increases the distributed path resistance below the buffer layer to eliminate the snapback phenomenon. In addition, the P-floating layer acts as an amplifying stage for the hole currents’ injection. The snapback-free structure features a half-cell pitch of 10 μm. For the same forward voltage drop, the turn-off loss of the MP-IGBT structure is reduced by 42%.

Low Turn-Off Loss Shorted-Anode IGBT with Multiple p+/n Collector

In this study, after numerical simulation, a novel snapback-free Shorted-Anode Insulated Gate Bipolar Transistor (SA-IGBT) with a Multiple p+/n Collector is proposed and investigated. This structure consists of P+ pillars located on the side of the collector. The P+ pillars provide high carrier injection efficiency and increase the anode resistance during the turn-on transient, eliminate the snapback phenomenon, and above all, they also extract holes during the turn-off process. This results in better performance between Eoff and Vce with the multiple p+/n collector (MPC) SA-IGBT and is advantageous for turn-off loss. When the MPC SA-IGBT and the SA-IGBT have the same forward voltage drop, the MPC structure reduces the turn-off loss by 25%.

Characteristics investigation on 4.5kV IGBT with partially narrow mesa and split-gate

Low on-state voltage and low turn-off loss are key issues for IGBT used in HVDC and FACTS. Partial narrow mesa was introduced to improve emitter side contact resistance of IGBT based on Nakagawa limit assumption. However, turn-off loss increases and short circuit sustainability get worse. Split gate separates gate electrode from drift region and reduces gate-collector capacitance to lower turn-off energy loss. Combination partial narrow mesa with split gate can get better gate performance and turn-off characteristics in 4.5kV IGBT. Simulated results with TCAD show proposed models improves switching loss and gate reliability. By adjusting split gap electric filed, split gate shape has an important effect on turn-on characteristics.

An Optimized Zero-Current, Zero-Voltage, and Three-Level DC–DC Converter

In this article, an optimized zero-voltage and zero-current pulsewidth modulation converter is proposed by investigating conventional converters widely used in dc grids. In this presented model, instead of using three-phase power switches, single-power switches are employed since single-power MOSFETs and IGBTs have lower switching loss and simpler drive circuit than the other module series. Therefore, the converter size and its power loss will decrease compared with the models with three-phase components. In addition, soft switching is utilized in the proposed converter to decrease the total power loss and increase efficiency accordingly. Also, for optimum use of zero-voltage switching (ZVS) and zero-current switching (ZCS), a new combination of IGBT and MOSFET is presented in the converter's circuit. Considering low turn-off loss for IGBT and low capacitive loss for MOSFET, IGBT and MOSFET are taken for ZVS switching and ZCS switching, respectively. In addition, a simple stabilizer circuit is added to the output part to improve the operation of the output filter since the filter plays an essential role in dc-dc converters. Finally, simulation of the proposed model is implemented in the PLECS software, and the results confirm the proper application of ZVS and ZCS, converter high efficiency, and high stability at the output voltage.

Simulation Study of an Ultralow Switching Loss p-GaN Gate HEMT With Dynamic Charge Storage Mechanism

In this article, a dynamic charge storage mechanism is proposed for designing the p-GaN gate dynamic charge storage high-electron-mobility transistor (DCS-HEMT) with ultralow switching loss. The device features a p-doped DCS layer in AlGaN buffer. When the DCS-HEMT is turning off, the net negative charges in the DCS layer significantly contribute to the depletion of 2-D-electron-gas (2DEG) channel, leading to low turn-off loss (${E} _{OFF}$ ). During turn-on process, reduction of the negative charges amount could accelerate the formation of electrons at the 2DEG channel, which results in low turn-on loss (${E} _{ON}$ ). Verified by the calibrated simulation, total switching loss (${E} _{\text {SW}} \boldsymbol = {E}_{OFF} +{E}_{ON}$ ) of the designed DCS-HEMT is 61% lower than that of the conventional p-GaN gate HEMT (C-HEMT). The improved performance makes the DCS-HEMT a competitive candidate for low switching loss power applications.

Soft-Switched Ultrahigh Gain DC–DC Converter With Voltage Multiplier Cell for DC Microgrid

In this article, a soft-switched modular nonisolated converter is proposed for distributed generation systems. By integrating flyback energy delivering circuit to the interleaved boost converter, ultrahigh-voltage gain and high efficiency are achieved with reduced duty ratio. Cockcroft-Walton based multiplier cell extensively reduces voltage stress on the active switches. Voltage spikes across mosfets caused by leakage inductance and interconnection of primary-secondary windings are alleviated by adjoining the active switch based auxiliary circuit. Thus, low voltage rating switches (small R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds(on)</sub> ) are employed. Furthermore, the clamp circuit realizes wide-load-range zero-voltage switching (ZVS) turn-on and, reduced falling current magnitudes ensures low turn-off losses for all the mosftets. Also, leakage-energy is recycled to the load. Indeed, leakage-energy effectively limits the rate of fall-current (di <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> /dt) through power diodes and alleviates the reverse-recovery problem by turning-off them with zero-current switching. Furthermore, during turn-on, ZVS is achieved for all the diodes. Thus, voltage spikes across the diodes are suppressed without needing any snubber. Minimized voltage stresses, lowered on-state and switching losses of the semiconductor devices, altogether, improves the efficiency. A 600-W prototype working at 100 kHz is developed in the laboratory to validate the design analysis. Measured efficiency at rated-load is 95.81% and maximum efficiency is 96.65%.

Soft-Switching Bridgeless Buck–Boost PFC Converter Using Single Magnetic Core

In this article, a new bridgeless single-phase buck-boost power factor correction (PFC) converter with one magnetic core is introduced. The proposed converter is designed to operate in discontinuous capacitor voltage mode (DCVM) to achieve low total harmonic distortion (THD) and continuous input current with a simple structure. The DCVM operation gives additional advantages, such as inherent PFC, low turn-off losses, and reduced complexity of the control circuitry. Unlike the buck converter, the proposed converter eliminates the dead angle of input current without adding any extra circuits. Also, by eliminating two input diodes in power flowing path, the efficiency is further improved. Due to achieved almost zero current switching at the turn-on and almost zero voltage switching at the turn-off, the switching losses are eliminated. In this article, theoretical analysis and principal operation of the converter are discussed. An experimental prototype is implemented to verify the performance of the proposed converter. Experimental results are presented for a 120-W prototype at 110-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> input and 48-V output.

Interleaved Isolated Single-Phase PFC Converter Module for Three-Phase EV Charger

This paper presents an interleaved isolated power factor correction (PFC) converter module for three-phase electric vehicle (EV) chargers requiring for wide output voltage ranges. The proposed circuit is comprised of two half-bridge (HB) voltage-fed isolated PFC converters with parallel-input-series -output structure, which is operated in interleaved discontinuous conduction mode (DCM). Due to zero-voltage and zero-current switching (ZV-ZVS) characteristics in the primary side, it is possible to operate IGBTs at a high frequency with several tens of kHz. Also, the voltage ratings of secondary devices can be reduced so that switching devices with low turn-off losses such as MOSFETs are available. The proposed converter has only single voltage loop and the harmonic regulation is accomplished by feed-forward compensation. The feasibility of the proposed PFC module has been verified with a 5 kW prototype.

A Novel IGBT With High-${k}$ Dielectric Modulation Achieving Ultralow Turn-Off Loss

A novel insulated gate bipolar transistor modulated by a high- ${k}$ dielectric (HK-IGBT) is presented. By laterally alternating the HK-pillar and N-drift, HK-IGBT can offer a quick and complete depletion to the drift region during the turn-off transient. This merit greatly reduces the current varying time of an HK-IGBT. Moreover, HK-IGBT can obtain a better electric field distribution, which enables the carrier stored layer (CSL) to have a higher doping dose when compared to a typical carrier stored trench gate bipolar transistor (CSTBT). These advantages improve the relationship between the static and transient power losses. According to the simulation results, HK-IGBT obtains a 66% lower turn-off loss than that of a field stop (FS) IGBT with the same ON-state voltage. Moreover, by using a CSL, the performance of an HK-IGBT can be comparable with that of a super-junction IGBT (SJ-IGBT).

A Novel Double-RESURF SOI-LIGBT With Improved $V_{\mathrm{\scriptscriptstyle ON}}-{E}_{ \mathrm{\scriptscriptstyle OFF}}$ Tradeoff and Low Saturation Current

A novel double-reduced surface field technique (RESURF) insulated gate bipolar transistor based on lateral insulated gate bipolar transistor based on silicon-on-insulator (SOI-LIGBT) with deep-trench-cathode and self-biased pMOS is proposed and investigated by numerical simulation. The proposed SOI-LIGBT remarkably features a deep trench, a self-biased pMOS, a carrier stored layer (n-CS), and p-shield region at the cathode side. Thanks to the n-CS, the proposed device achieves a low ON-state voltage ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ). And the doping concentration of the n-CS ( ${N}_{\text {CS}}$ ) has almost no impact on the breakdown voltage (BV). Benefited from the self-biased pMOS, the proposed device shows low saturation current and extended short-circuit current withstand-time. In addition, the proposed structure achieves a low turn-off loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). Simulation results reveal that, compared with the conventional double-RESURF SOI-LIGBT, the proposed structure achieves 15% ${V}_{ \mathrm{\scriptscriptstyle ON}}$ reduction and 50% saturation current reduction. In addition, the proposed device can sustain the short circuit current for 90% longer time than the conventional double-RESURF SOI-LIGBT.

Low Turn-Off Loss 4H-SiC Insulated Gate Bipolar Transistor With a Trench Heterojunction Collector

In this work, an improved 4H-SiC insulated gate bipolar transistor (IGBT), or CTH-IGBT, with a trench p-polySi/p-SiC heterojunction on the backside of the device is proposed to reduce the turn-off energy loss ( $E_{off}$ ) and turn-off time ( $T_{off}$ ). The electrical properties of the proposed and contrast structures are all simulated using the ATLAS simulation software to research the working mechanism of this improved structure. For the static performance, the specific ON-resistance ( $R_{on,sp}$ ) and the figure of merit ( ${\mathrm{ FOM}} = V_{BR}^{2}/ R_{on,sp}$ ) are not influenced much as compared to the traditional structure at the same breakdown voltage ( $V_{BR}$ ) of 12 kV. However, with a prominent electron current path formed by the heterojunction region of CTH-IGBT, a very available conduction path to discharge the electrons during turn-off process is proved in this article. The simulation results demonstrate that compared with the traditional structure, the turn-off energy loss of the CTH-IGBT is reduced by 76.4%, while the turn-off time is reduced by 85.0%.

Simulation Study of 4H-SiC Trench Insulated Gate Bipolar Transistor with Low Turn-Off Loss.

In this work, an insulated gate bipolar transistor (IGBT) is proposed that introduces a portion of the p-polySi/p-SiC heterojunction on the collector side to reduce the tail current during device turn-offs. By adjusting the doping concentration on both sides of the heterojunction, the turn-off loss is further reduced without sacrificing other characteristics of the device. The electrical characteristics of the device were simulated through the Silvaco ATLAS 2D simulation tool and compared with the traditional structure to verify the design idea. The simulation results show that, compared with the traditional structure, the turn-off loss of the proposed structure was reduced by 58.4%, the breakdown voltage increased by 13.3%, and the forward characteristics sacrificed 8.3%.