Low Trap-state Density Research Articles

Electrical properties in vanadyl-phthalocyanine-based metal-insulator-semiconductor devices

We investigated electrical properties of vanadyl phthalocyanine (VOPc) metal-insulator-semiconductor (MIS) devices by the measurement of capacitance and conductance, which were fabricated on ordered para-sexiphenyl (p-6P) layer by weak epitaxy growth method. The VOPc∕p-6P MIS diodes showed a negligible hysteresis effect at a gate voltage of ±20V and small hysteresis effect at a gate voltage of ±40V due to the low interface trap state density of about 1×1010eV−1cm−2. Furthermore, a high transition frequency of about 10kHz was also observed under their accumulation mode. The results indicated that VOPc was a promising material and was suitable to be applied in active matrix liquid crystal displays and organic logic circuits.

Enhanced Performance and Reliability for Solid-Phase Crystallized Poly- Si TFTs with Argon Ion Implantation

High-performance solid-phase crystallized (SPC) polycrystalline silicon thin-film transistors (TFTs) with argon ion implantation (argon-implanted poly- TFTs) are proposed in this study. Compared to the control poly- TFT, the argon-implanted poly- TFT has superior electrical characteristics, including lower threshold voltage, higher field-effect mobility, steeper subthreshold swing, lower trap state density, etc. These electrical performance improvements could be attributed to the fine microstructure of the SPC poly- film improved by deep argon ion implantation beyond the interface of amorphous and underlying oxide. Therefore, a high-quality poly- channel accompanied with larger grain size and lower grain boundary trap states could be obtained. Moreover, the argon-implanted poly- TFT also exhibits an improved hot-carrier stress immunity owing to reduced weak or bonds from fewer grain boundaries in the poly- channel.

Multigram scale synthesis and characterization of monodisperse tetragonal zirconia nanocrystals.

A new and simple method has been developed to synthesize large quantities of highly monodisperse tetragonal zirconia nanocrystals. In this synthesis, a nonhydrolytic sol-gel reaction between zirconium(IV) isopropoxide and zirconium(IV) chloride at 340 degrees C generated 4 nm sized zirconia nanoparticles. A high-resolution transmission electron microscopic (HRTEM) image showed that the particles have a uniform particle size distribution and that they are highly crystalline. These monodisperse nanoparticles were synthesized without any size selection process. X-ray diffraction studies combined with Rietveld refinement revealed that the ZrO(2) nanocrystals are the high-temperature tetragonal phase, and very close to a cubic phase. When zirconium(IV) bromide is used as a precursor instead of zirconium chloride, zirconia nanoparticles with an average size of 2.9 nm were obtained. The UV-visible absorption spectrum of 4 nm sized zirconia nanoparticles exhibited a strong absorption starting at around 270 nm. A fluorescence spectrum with excitation at 300 nm showed a broad fluorescence band centered around 370 nm. FTIR spectra showed indication of TOPO binding on the ZrO(2) nanoparticle surface. These optical studies also suggest that the nanoparticles are of high quality in terms of narrow particle size distribution and relatively low density of surface trap states.

Characteristics of low temperature poly-Si TFT device and circuits fabricated with disilane

Various fabrication techniques have been employed in order to optimize the performance of poly-Si TFTs device and circuits. We have prepared poly-Si active film by LPCVD and PECVD using monosilane and disilane recrystallized by the low temperature process of ELA and the high temperature process of SPC. The poly-Si TFTs with ELA active films exhibit higher field effect mobility and lower threshold voltages than those with SPC active film due to low intragranular trap state density. The poly-Si TFTs with active film deposited using Si2H6 exhibit higher mobility and sub-threshold slope than those with active film deposited using SiH4 due to larger poly-Si grain size and lower grain boundary trap state density. The oscillation frequency of a 23-stage CMOS inverter chain and the current driving capability of a CMOS transmission gate indicate that the low temperature processed circuits with active film deposited using Si2H6 and annealed by ELA method exhibit remarkable performances.

Influence of the Grain Boundaries and Intragrain Defects on the Performance of Poly‐Si Thin Film Transistors

The influence of grain boundaries and intragrain defects on poly‐Si thin‐film transistors (TFTs) was investigated by examining the crystallinity of poly‐Si films formed by solid phase crystallization (SPC) and excimer laser annealing (ELA), and the electrical characteristics of transistors fabricated on the poly‐Si films were examined. The increase in grain size by SPC improves field effect mobility (μFE) due to the increase in the emission current over the potential barrier height at the grain boundary. The decrease in intragrain defect densities by an oxide thinning process improves the μFE, threshold voltage (Vth) and subthreshold voltage swing (S). On the contrary, in spite of the small grain size of 800 Å, poly‐Si TFTs fabricated by ELA exhibit good characteristics with a high μFE, low Vth and low S, and good uniformity. It is found that since the realization of excellent performance and good uniformity in poly‐Si TFTs depends on a low trap state density at the grain boundaries and a low intragrain defect density, poly‐Si films formed by ELA are well suited for the application to poly‐Si TFT liquid crystal display with peripheral integrated circuits.

The Performance of Polycrystalline Silicon Thin film Transistors and CMOS Driving Circuits with Various Active Films

ABSTRACTThe performance of poly-Si TFTs and CMOS circuits with various active films prepared by different deposition processes and annealing methods, such as SPC(Solid Phase Crystallization) and ELA(Excimer Laser Annealing), have been investigated. We have examined the effects of DC characteristics of poly-Si TFT, such as mobility, threshold voltage and ON- OFF- current level, on the dynamic performance of the CMOS circuits.We have fabricated poly-Si TFT devices and CMOS circuits with various process conditions, such as active layer preparation source gases, annealing method, film thickness and source/drain impurity doping. The TFTs with ELA active films exhibit much higher field effect mobility and ON/OFF current ratio than those with SPC active film due to low intragranular trap state density. The TFTs with active film deposited using Si2H6 have higher mobility and sub-threshold slope than those with active film deposited using SiH4 because of the large poly-Si grain size and less grain boundary defects. We have observed that the device ON-current, mobility and VTH are the dominant characteristics to control the operation speed of CMOS circuits. We have also found that the effects of active film thickness and source/drain doping process on the performance of CMOS ring oscillator may not be neglected and that it should be optimized for AMLCD applications.

Characteristics of low-temperature and low-energy plasma-enhanced chemical vapor deposited SiO2

Deposition of high quality silicon dioxides was obtained at low temperatures by a specially designed plasma chemical vapor deposition (PECVD) system. The system employed a long quartz tube as a reactor and a set of three vertically standing plates for glow discharge. The deposited oxide, which employed a large amount of helium (He) to dilute silane (SiH4) and nitrous oxide (N2O) reactants, was observed to possess excellent qualities, as compared to those of thermally grown oxides. The chemical composition used for obtaining electrical integrities of the PECVD oxides was investigated. Additionally, the effects of post-metallization annealing on the oxides were investigated in detail. Oxides deposited at a substrate temperature of 250 °C were observed to possess a low interface trap state density (Dit) of only 3×1010 cm−2 eV−1 and low total trapped charge density (Qtotal) of 5.8×1016 cm−3. Those, however, which were deposited at 350 °C, have more stable electrical characteristics under current/voltage bias-temperature stress, but their Dit and Qtotal are around 2×1011 cm−2 eV−1 and 3.4×1016 cm−3, respectively. An atom-bonding model was proposed in this present work, according to physical, chemical, and electrical analyses in accounting for phenomena of charge-trapping and also in upgrading the electrical integrity of the deposited oxides. The applicability of these low-temperature oxides toward fabricating hydrogenated amorphous-silicon thin film transistor (a-Si:H TFT’s) was investigated. Adequate electrical performances of the TFT’s with a high on/off current ratio of more than 106 and high field effect mobility (μFET) of around 0.6 cm2/V s were obtained.