Low-power Processing Research Articles

CIM: A Novel Clustering-based Energy-Efficient Data Imputation Method for Human Activity Recognition

Human activity recognition (HAR) is an important component in a number of health applications, including rehabilitation, Parkinson’s disease, daily activity monitoring, and fitness monitoring. State-of-the-art HAR approaches use multiple sensors on the body to accurately identify activities at runtime. These approaches typically assume that data from all sensors are available for runtime activity recognition. However, data from one or more sensors may be unavailable due to malfunction, energy constraints, or communication challenges between the sensors. Missing data can lead to significant degradation in the accuracy, thus affecting quality of service to users. A common approach for handling missing data is to train classifiers or sensor data recovery algorithms for each combination of missing sensors. However, this results in significant memory and energy overhead on resource-constrained wearable devices. In strong contrast to prior approaches, this paper presents a clustering-based approach (CIM) to impute missing data at runtime. We first define a set of possible clusters and representative data patterns for each sensor in HAR. Then, we create and store a mapping between clusters across sensors. At runtime, when data from a sensor are missing, we utilize the stored mapping table to obtain most likely cluster for the missing sensor. The representative window for the identified cluster is then used as imputation to perform activity classification. We also provide a method to obtain imputation-aware activity prediction sets to handle uncertainty in data when using imputation. Experiments on three HAR datasets show that CIM achieves accuracy within 10% of a baseline without missing data for one missing sensor when providing single activity labels. The accuracy gap drops to less than 1% with imputation-aware classification. Measurements on a low-power processor show that CIM achieves close to 100% energy savings compared to state-of-the-art generative approaches.

Design of a Self-Organizing Routing Protocol for Underwater Wireless Sensor Networks Based on Location and Energy Information

Underwater wireless sensor networks (UWSNs) are significantly different from terrestrial sensor networks in the following aspects: low bandwidth, high latency, variable topology, limited battery, low processing power and so on. These new features pose many challenges to the design of self-organizing routing protocol for UWSNs. This paper focuses on the application of Ad Hoc On-demand Distance Vector (AODV) routing protocol in UWSNs. In order to solve the problems of packet collision and excessive energy consumption associated with the flooding-based routing discovery method and the periodic hello packet routing maintenance mechanism of AODV, a routing discovery and maintenance method based on location and energy information is proposed, and it is referred to as the route-focusing AODV (RFAODV) routing protocol. In the RFAODV protocol, the routing discovery process is focused on a few nodes through forwarding area control and dynamic delay adjustment. In addition, feedback from a media access control layer and residual energy control are used for routing maintenance. We implement the RFAODV and evaluate its performance according to the sea trial data as parameters in the NS-2. The simulation results show that compared with the other protocols, RFAODV improves the routing discovery success ratio by at least 18%, increases the packet transmission ratio by at least 4%, reduces the protocol overhead by at least 15% and reduces the energy consumption by at least 5% under various simulation scenarios. RFAODV is suitable for large-scale, high-load and dynamic networks underwater wireless sensor networks.

An Efficient Design of Multiplier for Using in Nano-Scale IoT Systems Using Atomic Silicon

Because of recent technological developments, such as Internet of Things (IoT) devices, power consumption has become a major issue. Atomic silicon quantum dot (ASiQD) is one of the most impressive technologies for developing low-power processing circuits, which are critical for efficient transmission and power management in micro IoT devices. On the other hand, multipliers are essential computational circuits used in a wide range of digital circuits. Therefore, the multiplier design with a low occupied area and low energy consumption is the most critical expected goal in designing any micro IoT circuits. This paper introduces a low-power atomic silicon-based multiplier circuit for effective power management in the micro IoT. Based on this design, a 4×4-bit multiplier array with low power consumption and size is presented. The suggested circuit is also designed and validated using the SiQAD simulation tool. The proposed ASiQD-based circuit significantly reduces energy consumption and area consumed in the micro IoT compared to most recent designs.

A neuromorphic bionic eye with broadband vision and biocompatibility using TIPS-pentacene-based phototransistor array retina

Taking inspiration from the human eye's information processing capabilities, the artificial optoelectronic neuronic device (AOEND) offers a promising approach to creating a bionic eye that performs real-time, low-power processing by integrating optical sensors, signal processing, and electronic neurons into a single device. Despite significant advancements, the current AOEND still faces challenges in terms of power consumption, flexibility, bio-compatibility, and, most importantly, achieving photo-sensitivity across the same broadband perceivable wavelength range (380nm to 740nm) as the human eye. In this study, we present a commercially ready, dual-gated thin-film-transistor (TFT)-based AOEND. Our device exhibits exceptional photo-response to specific wavelengths by utilizing an organic TIPS-pentacene material as the channel layer and intentionally tailoring its optical bandgap to approximately 1.6eV. Additionally, the device successfully replicates various photon-triggered synaptic characteristics and performs visual sensing, memory processing, and other functions with low power consumption. Our findings present a viable strategy for the development of future integrated sensing-memory-processing flexible devices for optoelectronic artificial retina perception applications.

In-situ artificial retina with all-in-one reconfigurable photomemristor networks

Despite that in-sensor processing has been proposed to remove the latency and energy consumption during the inevitable data transfer between spatial-separated sensors, memories and processors in traditional computer vision, its hardware implementation for artificial neural networks (ANNs) with all-in-one device arrays remains a challenge, especially for organic-based ANNs. With the advantages of biocompatibility, low cost, easy fabrication and flexibility, here we implement a self-powered in-sensor ANN using molecular ferroelectric (MF)-based photomemristor arrays. Tunable ferroelectric depolarization was intentionally introduced into the ANN, which enables reconfigurable conductance and photoresponse. Treating photoresponsivity as synaptic weight, the MF-based in-sensor ANN can operate analog convolutional computation, and successfully conduct perception and recognition of white-light letter images in experiments, with low processing energy consumption. Handwritten Chinese digits are also recognized and regressed by a large-scale array, demonstrating its scalability and potential for low-power processing and the applications in MF-based in-situ artificial retina.

Analogue Artificial Synaptic Performance of Self‐Rectifying Resistive Switching Device

AbstractThe immense increase of unstructured data require novel computing systems that can process the input data with low power and parallel processing. This functionality is similar to that of human brains that are composed of numerous neurons, synapses, and their complex connections. To mimic the functionality of the human brain with an electronic device, the resistive switching device and crossbar array has attracted considerable attention for artificial synaptic devices and integrated systems, respectively. For this purpose, the self‐rectifying resistive switching cell based on the Si:ZrOx thin film is developed and its reliability characteristics are tested. Four achievements are highlighted in this study. 1) The retention characteristic is improved by the adoption of TaOx thin film as an oxygen reservoir layer. 2) The asymmetric electrodes can make the self‐rectifying resistive cell (SRC) have sufficient rectifying characteristic. 3) The linearity of conductance update has a dominant effect on the inference performance compared to that of the conductance range variation. 4) The device of the interface‐type resistive switching shows a high enough device yield in the crossbar array device and exhibits reliable multiply‐and‐accumulate operations in the crossbar array to mimic the human brain‐inspired computing system.

Scalable and ultralow power silicon photonic two-dimensional phased array

Photonic integrated circuit based optical phased arrays (PIC-OPAs) are emerging as promising programmable processors and spatial light modulators, combining the best of planar and free-space optics. Their implementation on silicon photonic platforms has been especially fruitful. Despite much progress in this field, demonstrating steerable two-dimensional (2D) OPAs that are scalable to a large number of array elements and operate with a single wavelength has proven a challenge. In addition, the phase shifters used in the array for programming the far-field beam are either power hungry or have a large footprint, preventing the implementation of large scale 2D arrays. Here, we demonstrate a two-dimensional silicon photonic phased array with high-speed (∼330 kHz) and ultralow power microresonator phase-shifters with a compact radius (∼3 µm) and 2π phase shift ability. Each phase-shifter consumes an average of ∼250 µW of static power for resonance alignment and ∼50 µW of power for far-field beamforming, a more than one order of magnitude improvement compared to prior OPA works based on waveguide-based thermo-optic phase shifters. Such PIC-OPA devices can enable a new generation of compact and scalable low power processors and sensors.

Mechanism for Cloud Computing Enviroment's Reliable Au-thenticated Token Handling

Cloud computing (CC) has matured in terms of dependability and effectiveness, which has led to the migration of many applications to the cloud. Three-factor Multilateral Authenticity and Knowledge Acceptance (MAKA) mechanisms for multi-server systems are gaining a lot of interest for their convenience and security. Although there are many extant three-factor MAKA protocols, none of them give a rigorous secure guarantee, making them vulnerable to numerous assaults on other procedures in the chain. And most three-factor MAKA mechanisms lack adaptive cancellation mechanisms, preventing malevolent users from being quickly removed. We present a three-factor MAKA protocol with a proven adaptive reversible evidence in the arbitrary source to overcome these issues. This method uses Schnorr identities to enable vibrant administration by the client. In multi-server setups, our procedure is capable of meeting a wide range of requirements. For intelligent systems with low processing power, the suggested method is a viable option. The entire computation code demonstrates the system's viability.

Vision-based techniques for automatic marine plankton classification

Plankton are an important component of life on Earth. Since the 19th century, scientists have attempted to quantify species distributions using many techniques, such as direct counting, sizing, and classification with microscopes. Since then, extraordinary work has been performed regarding the development of plankton imaging systems, producing a massive backlog of images that await classification. Automatic image processing and classification approaches are opening new avenues for avoiding time-consuming manual procedures. While some algorithms have been adapted from many other applications for use with plankton, other exciting techniques have been developed exclusively for this issue. Achieving higher accuracy than that of human taxonomists is not yet possible, but an expeditious analysis is essential for discovering the world beyond plankton. Recent studies have shown the imminent development of real-time, in situ plankton image classification systems, which have only been slowed down by the complex implementations of algorithms on low-power processing hardware. This article compiles the techniques that have been proposed for classifying marine plankton, focusing on automatic methods that utilize image processing, from the beginnings of this field to the present day.

A novel state of health estimation approach based on polynomial model for lithium-ion batteries

Energy management systems are one of the most critical components in a battery unit's safe and efficient operation. Many measurable or calculable parameters, such as voltage, current, capacity, and internal resistance, are considered when designing energy management systems. Parameters that cannot be measured or are costly to measure, such as battery state of charge (SOC) or battery health state (SOH), can be determined by estimation. SOH, which can be used as both an input and an output parameter for EMS, is an essential parameter for the long-life and high-efficiency use of the battery. Two different approaches, experimental-based and model-based, are used for SOH estimation. Experimental-based methods need all the real-time data of the batteries, which is caused the requirement of a very long time and data storage. The adaptive filtering technique, which is a model-based technique, requires a complete and accurate model of the battery. The nonlinear electrochemical structures of batteries make modeling difficult. On the other hand, optimization-based methods, a data-driven technique, need very high processing power to find the optimal result. In addition, separate data is needed for training and testing in machine learning-based methods and requires high processing power. Contrary to these disadvantages, high-accuracy predictions can be made using low processing power and very little data in the experimental curve fitting technique. In this study, experimental and curve-fitting-based SOH estimation is proposed by using polynomial-based system identification techniques. Polynomial-based identification methods can model the system with high accuracy, low cost, and low processing power. Battery degradation dataset belonging to Oxford University is used. In the aforementioned dataset, the general model inference is made using only %1 of the entire cycle life of the battery. Obtained proposed model's results were compared with different methods in the literature in terms of RMSE, and its superiority was demonstrated.

Multi-objective edge server placement using the whale optimization algorithm and game theory

Due to the users’ mobility, new online applications, as well as low processing power and limited energy of smart devices, traditional cloud computing models could not provide new required services. Cloud service providers improve the quality of their services by moving some servers to the edge of the network and closer to mobile users. Considering the moving nature of users and the heterogeneous service demands in different areas, the optimal placement of servers plays an important role in increasing the quality of service provided to users. However, because of the large number of servers, finding the optimal location of these resources is a serious challenge. In the proposed method of this paper (MES-WG), in the first step, the geographical area of server deployment is divided into smaller sub-regions to reduce the complexity of the problem. Then, by using the WOA algorithm the search agent finds the optimal location of the servers. In the next step, a neural network is used for the local placement of all servers in each area. Finally, game theory is deployed for the convergence of resource placement in all sub-regions. The experimental results show that the proposed method reduces the network latency by 33.5% and also improves the load balance on servers by 28.2%, compared to some of the state-of-the-art methods.

Implementation of Precision Machine Tool Thermal Error Compensation in Edge-Cloud-Fog Computing Architecture

Abstract The implementation of precision machine tool thermal error compensation in edge-cloud-fog computing architecture has the potential to control the thermal error. However, the challenges faced by the successful implementation are described as follows: The data collection and transfer efficiency are low, and the control accuracy is not deficient. To address these challenges, a hardware design scheme is proposed for the high-performance intelligent gateway node based on the low-power processor architecture of ARM Cortex-A7. Moreover, a new transformer-improved-gate long short-term memory model is proposed, and then it is embedded into edge-cloud-fog computing architecture. With the implementation of gear profile grinding machine thermal error compensation in edge-cloud-fog computing architecture, the maximum values of the tooth profile tilt deviation are reduced from 17.4 μm to 5.4 μm and from 17.9 μm to 5.8 μm for the left and right tooth flanks, respectively. Moreover, the maximum values of the tooth profile deviation are reduced from 18.9 μm to 6.1 μm and from 18.2 μm to 5.8 μm for the left and right tooth flanks, respectively. Compared with the traditional collection mode, the response delay of the designed intelligent gateway in the acquisition mode is reduced by 40%.

Self-Supervised Pre-Training Joint Framework: Assisting Lightweight Detection Network for Underwater Object Detection

In the computer vision field, underwater object detection has been a challenging task. Due to the attenuation of light in a medium and the scattering of light by suspended particles in water, underwater optical images often face the problems of color distortion and target feature blurring, which greatly affect the detection accuracy of underwater object detection. Although deep learning-based algorithms have achieved state-of-the-art results in the field of object detection, most of them cannot be applied to practice because of the limited computing capacity of a low-power processor embedded in unmanned underwater vehicles. This paper proposes a lightweight underwater object detection network based on the YOLOX model called LUO-YOLOX. A novel weighted ghost-CSPDarknet and simplified PANet were used in LUO-YOLOX to reduce the parameters of the whole model. Moreover, aiming to solve the problems of color distortion and unclear features of targets in underwater images, this paper proposes an efficient self-supervised pre-training joint framework based on underwater auto-encoder transformation (UAET). After the end-to-end pre-training process with the self-supervised pre-training joint framework, the backbone of the object detection network can extract more essential and robust features from degradation images when retrained on underwater datasets. Numerous experiments on the URPC2021 and detecting underwater objects (DUO) datasets verify the performance of our proposed method. Our work can assist unmanned underwater vehicles to perform underwater object detection tasks more accurately.

A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation

Low-power deep learning accelerators (DLAs) on the speech processing enable real-time applications on edge devices. However, most of the existing accelerators suffer from high-power consumption and focus on image applications only. This article presents a low-power accelerator for speech separation through algorithm and hardware optimizations. At the algorithm level, the model is compressed with structured sensitivity as well as unstructured pruning, and further quantized to the shifted 8-bit floating-point format instead of the 32-bit floating-point format. The computations with the zero kernel and zero activation values are skipped by decomposition of the dilated and transposed convolutions. At the hardware level, the compressed model is then supported by an architecture with eight independent multipliers and accumulators (MACs) with a simple zero-skipping hardware to take advantage of the activation sparsity and low-power processing. The proposed approach reduces the model size by 95.44% and computation complexity by 93.88%. The final implementation with the TSMC 40-nm process can achieve real-time speech separation and consumes 1.6-mW power when operated at 150 MHz. The normalized energy efficiency and area efficiency are 2.344 TOPS/W and 14.42 GOPS/mm2, respectively.

Design of K-Band Power Amplifier with 180-Degree Phase- Shift Function Using Low-Power CMOS Process

In this study, a K-band complementary metal oxide semiconductor (CMOS) power amplifier was designed using a low-power (LP) process to improve the integration of the beamforming system. In order to reduce the overall system size, a 180° phase-shift function was mounted. It was designed in a four-stage structure to secure sufficient gain. In addition, we propose a way to secure wideband characteristics by utilizing the gains of each of the four stages. The power amplifier was designed with a 40-nm LP CMOS process to verify the feasibility of the proposed technique. The measured P1dB for 0° and 180° phase-shift modes were 15.25 dBm and 14.30 dBm, respectively, at the operating frequency of 25.0 GHz. The measured phase difference between the two modes was 217° at the 25.0 GHz.

DESIGN SPACE EXPLORATION OF LOW POWER FULL ADDER ACROSS MULTIPLE LOGIC STYLES AND PROCESS

The signal processing in digital domain becoming ubiquitous, a full adder circuit module has gained prominence for its optimization in terms of its speed, power dissipation, noise margin and area. Further, with the advent of mobile applications on electronic devices, low power has emerged as an overriding design criterion. The proposed work aims to explore the design space of a low power full adder circuit and the implications of logic styles on power-delay trade-offs. Further, the issues impacting the selection of process for design for a given application are addressed. A 1-bit full adder circuit in static CMOS logic style and hybrid logic style is designed and optimized for low-power by carrying out exhaustive simulations using the LT spice simulator in 65 nm and 45 nm standard process to explore their power envelope, before low power process becomes necessary for design. Low power designs are demonstrated and the trade-offs with speed and area are explored.

Emerging AI Technologies Inspiring the Next Generation of E-Textiles

The smart textile and wearables sector is looking towards advancing technologies to meet both industry, consumer and new emerging innovative textile application demands, within a fast paced textile industry. In parallel, inspiration based on the biological neural workings of the human brain is driving the next generation of Artificial Intelligence (AI). AI inspired hardware (neuromorphic computing) and software modules mimicking the processing capabilities and properties of neural networks and the human nervous system are taking shape. The textile sector needs to actively look at such emerging and new technologies, taking inspiration from their workings and processing methods in order to stimulate new and innovative embedded intelligence advancements in the e-textile world. This emerging next generation of AI is rapidly gaining interest across varying industries (textile, medical, automotive, aerospace, military). It brings the promise of new innovative applications enabled by low size, weight and processing power technologies. Such properties meet the need for enhanced performing integrated circuits (IC’s) and complex machine learning algorithms. How such properties can inspire and drive advancements within the e-textiles sector needs to be considered. This paper will provide an insight into AI advancements in the e-textiles domain, before focusing specifically on the future vision and direction around the potential application of neuromorphic computing and spiking neural network inspired AI technologies within the textile sector. We investigate the core architectural elements of artificial neural networks, neuromorphic computing (2D and 3D structures) and how such neuroscience inspired technologies could impact and inspire change and new research developments within the e-textile sector.

DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC

3-D red, green, blue, and depth (RGB-D) and 3-D perception are essential information for 3-D applications such as autonomous driving and augmented reality (AR)/virtual reality (VR) systems. However, battery- and resource-limited mobile devices face difficulties in obtaining dense RGB-D data and 3-D perception information in low-power (LP) and real-time. Specifically, an RGB-D sensor is used to acquire 3-D RGB-D data, but it consumes high power and produces sparse depth data. Moreover, preprocessing for RGB-D data requires a long execution time. Previous 3-D perception accelerators also have limited reconfigurability, making them incapable of executing diverse 3-D perception tasks. In this article, an LP and real-time depth signal processing system-on-chip (SoC), depth signal processing unit (DSPU), is presented. The DSPU produces accurate dense RGB-D data using a convolutional neural network (CNN)-based monocular depth estimation (MDE) and a sensor fusion with an LP ToF sensor. Then, the DSPU performs 3-D perception inferring a point cloud-based neural network (PNN). The DSPU executes the depth signal processing system with the following features: 1) a unified point processing unit (UPPU) with a flexible window based-search algorithm for simplifying the complexity of point processing algorithms and saving the arithmetic units and buffers; 2) a unified matrix processing unit (UMPU) with bit-slice-level sparsity exploitation to accelerate various matrix processing algorithms; 3) a band matrix encoder and decoder to decrease the data transactions in the conjugate-gradient (C-Grad) method; and 4) a point feature (PF) reuse method with a pipelined architecture for low-latency and LP PNN inference. Finally, the DSPU achieves real-time implementation with 281.6 mW of the end-to-end 3-D B-box extraction system.

Personal computer usage and teasing among geographic information systems students

This study arose from the observation of teasing among Geographic Information Systems (GIS) students who use personal computers (PCs) during practical sessions. A review of the literature did not provide any informative knowledge on teasing based on PC characteristics. Hence, the study sought to assess the degree of teasing among GIS students, PC characteristics students are frequently teased over, types of teasing, and its positive and negative effects. Students at University of Education in Winneba (UEW), Ghana, provided data on their experiences with analysis employed being multinomial regression, binary logistic regression, the McNemar and Wilcoxon signed-rank test. The findings of the study revealed that students had experienced and engaged in various forms of teasing during GIS sessions. Low processing power of PCs and the brand type were the targets of verbal jokes among students. Teasing during lecture periods resulted in both positive and negative utility, with a greater number of students reporting net positive utility. Although the findings verified the researchers' utilitarian viewpoint, teasing needs to be regulated, as some students exhibited feelings of depression and low self-worth.

Honeynet Implementation in Cyber Security Attack Prevention with Data Monitoring System Using AI Technique and IoT 4G Networks

Cyber Physical Systems (CPS) comprises of the ubiquitous object concept those are connected with Internet to provide ability of data transmission and sensing over network. The smart appliances transmits the data through CPS devices with the implementation of Internet of Things (IoT) exhibits improved performance characteristics with significant advantages such as time savings, reduced cost, higher human comfort and efficient electricity utilization. In the minimal complexity sensor nodes cyber physical system is adopted for the heterogeneous environment for the wireless network connection between clients or hosts. However, the conventional security scheme uses the mechanisms for desktop devices with efficient utilization of resources in the minimal storage space environment, minimal power processing and limited energy backup. This paper proposed a Secure Honeynet key authentication (SHKA) model for security attack prevention through effective data monitoring with IoT 4G communication. The proposed SHKA model uses the lightweight key agreement scheme for authentication to provide security threats and confidentiality issues in CPS applications. With the implementation of SHKA HoneyNet model the data in IoT are monitored for security mechanism in IoT environment. The middleware module in SHKA scheme uses the Raspberry platform to establish internetworking between CPS device to achieve dynamic and scalability. The secure IoT infrastructure comprises of flexible evaluation of user-centric environment evaluation for the effectiveness. The developed SHKA model perform mutual authentication between CPS devices for minimal computation overhead and efficiency. The wireless channel uses the dynamic session key for the secure communication for cyber-attacks security with lightweight security in CPS system. The SHKA model demonstrate the effectiveness based on consideration of three constraints such as low power processing, reduced storage and minimal backup energy. Experimental analysis stated that proposed SHKA scheme provides lightweight end-to-end key establishment in every session. The CPS devices generates the session key of 128 bit long. The minimum key size is implemented to provide effective security in IoT 4G communication with minimal execution time. The simulation results demonstrated that SHKA model exhibits effective cyber-attacks for the constraint devices to improve performance of IoT network.