Low Parasitic Effects Research Articles

Application of five-phase PM synchronous machines in electrical traction drive systems

Three-phase electrical machines in traction applications on electrified passenger cars are operated in inverter-fed operation over wide speed ranges. With a high dynamic e-machine control and the operation with inverter switching frequencies above 10 kHz, high performance requirements can be achieved in terms of high drive dynamics, optimum operating points (⇒ system efficiency optimizations), satisfying torque accuracies and low parasitic effects (e.g., current ripple, harmonic losses, pulsating torques and magnetic noise). For these applications five-phase permanent magnet synchronous machines with a dual frequency operation can be drawn into account for an increase of the cost-benefit ratio on drive system level and further system benefits. In this contribution some base considerations regarding e-machine design and motor control are presented. The application of a third harmonic injection and the gained benefit is shown for a built-up and measured e-machine sample.

Electronically tunable grounded immittance simulators using an EX-CCCII

ABSTRACT In this paper, electronically tunable grounded immittance simulators are presented. Each of the proposed circuits employs a single Extra X Current Controlled Current Conveyers (EX-CCCII) and a single grounded capacitor. First, two circuits provide lossless positive grounded inductance. These circuits offer different lossless/lossy immittance circuits with some changes in the connection at the Z-terminals of EX-CCCII. The circuits do not require any constraint for component matching and exhibit low parasitic effects. The circuits can be tuned electronically by varying the bias current of EX-CCCII. As application examples, some of the proposed circuits are used to realise a tunable second-order band-pass filter and a tunable high pass filter. The functionality of the proposed immittance simulators is verified through PSPICE simulation using 0.25µm TSMC CMOS technology parameters. The experimental results are also included using commercially available IC’s AD-844.

Systematic transient characterisation of graphene NEMS switch for ESD protection

Integrated circuits (ICs) require robust and low-parasitic on-chip electrostatic discharging (ESD) protection. Compared to conventional in-Si PN-junction-based ESD protection structures, a novel above-IC graphene nanoelectromechanical system (NEMS) switch (gNEMS) ESD protection structure features low parasitic effects and superior current and heat handling capability. This work reports a systematic transient characterisation of gNEMS ESD switches by transmission line pulse (TLP) measurement for human body model ESD protection, revealing transient ESD discharging behaviours related to device dimensions and TLP pulse shapes. It provides practical design guidelines for using gNEMS switch as on-chip ESD protection for ICs. Unlike in-Si ESD protection structures, the new gNEMS ESD switch devices can be made in the back-end-of-line of ICs through three-dimensional heterogeneous integration.

On the Way from Fan-out Wafer to Fan-out Panel Level Packaging

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Manufacturing is currently done on wafer level up to 12″/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18″×24″ or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.

The electro-mechanical responses of suspended graphene ribbons for electrostatic discharge applications

This work presents a suspended graphene ribbon device for electrostatic discharge (ESD) applications. The device structure was proposed and fabricated after careful design considerations. Compared to the conventional ESD devices such as diodes, bipolar junction transistors, and metal-oxide-semiconductor field effect transistors, the proposed device structure is believed to render several advantages including zero leakage, low parasitic effects, fast response, and high critical current density. A process flow was developed for higher yield and reliability of the suspended graphene ribbons. Direct current (DC) and transmission-line pulse (TLP) measurements were carried out to investigate the switching behavior of the device, which is crucial for ESD operation. DC measurements with a different configuration were used to assess the mechanical shape evolution of the graphene ribbon upon biasing. Finite Element Simulations were conducted and agreed well with the experimental results. Furthermore, the current carrying capability of non-suspended graphene ribbons was tested using TLP. It was found that the critical current density of graphene is higher than that of copper wires widely used as interconnects in integrated circuits (ICs).

Flip-Chip Packaging of Low-Noise Metamorphic High Electron Mobility Transistors on Low-Cost Organic Substrate

The rapid growth of high-frequency wireless communication demands high-performance packaging structures at low cost. A flip-chip interconnect is one of the most promising technologies owing to its low parasitic effect and high performance at high frequencies. In this study, the in-house fabricated In0.6Ga0.4As metamorphic high electron mobility transistor (mHEMT) device was flip-chip-assembled using a commercially available low-cost organic substrate. The packaged device with the optimal flip-chip structure exhibited almost similar DC and RF results to the bare die. An exopy-based underfill was applied to the improvement of reliability with almost no degradation of the electrical characteristics. Measurement results revealed that the proposed packaging structure maintained a low minimum noise figure of 3 dB with 6 dB associated gain at 62 GHz. Such a superior performance after flip-chip packaging demonstrates the feasibility of the proposed low-cost organic substrate for commercial high-frequency applications up to the W-band.

An improved passive inductor microwave performance on gallium nitride substrates using ion implantation technology

Recently, gallium nitride (GaN) substrates have been widely used in high-power monolithic microwave integrated circuit applications, which work because of the high breakdown voltage associated with the wider energy band-gap. The objective of this article is to investigate the spiral inductors that have been used to implant various ions on GaN substrates, demonstrated separately by N+, Mg+ and O+. The measured substrate resistance (R sub) results were 85 Ω and 360 Ω for undoped GaN substrates and N+ doped substrates, respectively. This ion implantation technology could substantially improve the substrate resistance and provide a higher quality factor value (Q-value) for spiral inductors. The low parasitic effect extracted by the scattering parameter (S-parameter) for various substrates indicated that the spiral inductor value can be applied stably at high frequency. Consequently, the high GaN substrate quality adopting high-isolation ion implantation technology, demonstrates its huge potential for high-power and high-efficiency amplifier applications.

On the Realization of Simulated Inductors with Reduced Parasitic Impedance Effects

In this paper, a method for reducing the parasitic impedance effects of the current feedback operational amplifiers (CFOAs) in an inductor simulator at low frequencies is proposed. Also, two novel grounded inductors employing a current follower (CF) and a second generation current conveyor (CCII) are given to illustrate the parasitic reduction technique clearly. The low frequency restrictions of the proposed inductors due to terminal parasitic resistances can be improved by using the presented parasitic impedance reduction technique. SPICE simulations show that the presented inductor employing CFOAs in a voltage-mode (VM) band-pass and high-pass filter application has lower parasitic effects at low frequencies. In addition to simulation results, experimental test results are given to verify the theory.

SIMULTANEOUS SWITCHING NOISE MITIGATION CAPABILITY WITH LOW PARASITIC EFFECT USING APERIODIC HIGH-IMPEDANCE SURFACE STRUCTURE

A novel design with low parasitic effect for eliminating the simultaneous switching noise (SSN) in high-speed circuits is proposed by using the aperiodic high-impedance surface (A-HIS) structure. The A-HIS configuration is proposed in this work, revealing suppression of the SSN from 1.1∼ 1.85 GHz. It is shown that the HIS structure with aperiodic design, the SSN will be effectively suppressed. The undesired resonances of the proposed A-HIS structure are less than that of the conventional structure below 1 GHz. Less undesired peaks will ensure the electromagnetic interference (EMI) and signal integrity (SI). The measured results show very well compared with the conventional periodical HIS structures. The suppression results of the proposed A-HIS structure is checked by both measurement and simulation results. By using this proposed method, the simplicity of the structure is easier to fabricate as well as to route signal lines with a perfect power/ground planes. In addition, the proposed designs provide excellent SSN suppression and good signal integrity (SI) as the conventional structure.

Cost-Effective Chip-On-Heat Sink Leadframe Package for 800-Mb/s/Lead Applications

Chip-on-heat sink leadframe (COHS-LF) packages offer a simple, low-cost chip encapsulation structure with advanced electrical and thermal performance for high-speed integrated circuit applications. The COHS-LF package is a novel solution to the problems of increased power consumption and signal bandwidth demands that result from high-speed data transmission rates. Not only does it offer high thermal and electrical performance, but also provides a low-cost short time-to-market package solution for high-speed applications. In general, there are two main memory packages employed by the most popular high-speed applications, double data rate (DDR) SDRAM. One is the cheaper, higher parasitic leadframe packages, such as the thin small outline packages (TSOPs), and the other is the more expensive, lower parasitic substrate-based packages, such as the ball grid array (BGA). Due to the requirement for higher ambient temperature and operating frequency for high-speed devices, DDR2 SDRAM packages were switched from conventional TSOPs to more expensive chip-scale packages (i.e., BGA) with lower parasitic effects. And yet, by using an exposed heat sink pasted on the surface of the chip and packed in a conventional leadframe package, the COHS-LF is a simpler, lower cost design. Results of a three-dimensional full-wave electromagnetic field solver and SPICE simulator tests show that the COHS-LF package achieves less signal loss, propagation delay, edge rate degradation, and crosstalk than the BGA package. Furthermore, transient analysis using the wideband T-3/spl pi/ models optimized up to 5.6 GHz for signal speeds as high as 800 Mb/s/lead demonstrates the accuracy of the equivalent circuit model and reconfirms the superior electrical characteristics of COHS-LF package.

Effect of filler content on the dielectric properties of anisotropic conductive adhesives materials for high-frequency flip–chip interconnection

The dielectric property of anisotropic conductive film (ACF) as an interconnect materials in the flip–chip joints is becoming important concern for device packaging solution at high-frequency due to low parasitic effect on the signal transfer. The effects of non-conductive, dielectric filler content on dielectric properties of ACA materials, like dielectric constant, loss factor and loss tangent, and conductivity at high-frequency were investigated. Frequency is dominating factor in determining dielectric constant, loss factor, and conductivity. However, the filler content is dominant only on dielectric constant, not on the loss factor, and conductivity at low-frequency range. The effect of low dielectric constant (low- k) filler addition on high-frequency behavior of ACF interconnection in flip–chip assembly was also investigated. Impedance parameters of low- k ACF with Ni filler and low- k SiO 2 filler extracted from measurement were compared with that of conventional ACF with only Ni filler. The resonant frequency of conventional ACF flip–chip interconnect was 13 GHz, while the resonant frequency of low- k ACF including low- k SiO 2 filler was found at 15 GHz. This difference is originated from capacitance decrease of polymer matrix between bump and substrate pad due to change in dielectric constant of polymer matrix, which was verified by measurement-based modeling. The high-frequency property of the conductive adhesive flip–chip joint, such as resonant frequency can be enhanced by low- k polymer matrix.

Electrical Characterization of BCB for Electrostatic Microelectromechanical Devices

ABSTRACTElectrical properties and thickness of insulating dielectric films directly affect electrical energy loss and electrical breakdown limit in electric micromachines. A thick, low-k film exhibits low parasitic capacitive effects that help with the reduction of electrical energy loss. The electrical performance can be deteriorated due to degradation of the electrical properties of the insulating dielectric material caused by process, device structure, and moisture. In this paper, we introduce the application of CYCLOTENE, a spin-on, low-k, BCB-based polymer in electric micromachines as insulating layer and interlevel dielectric. A novel approach using interdigitated capacitors for electrical characterization of CYCLOTENE and the effect of moisture absorption is introduced in this paper. The dielectric constant of CYCLOTENE is extracted from two steps of capacitance measurements, giving an average value of 2.49 with a standard deviation of 1.5 %. The dielectric constant increases by 1.2 % after a humidity stress of 85 %RH at 85 °C. The measured I-V characteristics of CYCLOTENE show a dependency of the breakdown strength and leakage current on the geometrical dimensions of the device under test. A breakdown strength of 225 V/μm for 2 μm finger spacing and 320 V/μm for 3 μm finger spacing, and a leakage current of a few to tens of pA are measured. The I-V characteristics degrades drastically after a humidity stress of 85 %RH at 85 °C, showing a breakdown strength of 100 V/μm for 2 μm finger spacing and 180 V/μm for 3 μm finger spacing. Based on the results of this study, it is expected that the electrical efficiency of an electric micromachine is improved using BCB-based polymers with negligible dependency on moisture absorption. On the other hand, the maximum performance that depends on the maximum operating voltage is adversely affected by the degradation of the breakdown voltage after moisture absorption.

A new pad-oriented multiple-mode ESD protection structure and layout optimization

This work reports a new multiple-mode pad-oriented electrostatic discharge (ESD) protection structure, which protects input-output pads against ESD pulses of all modes. A unique pad-based quasi-symmetric layout design is devised to improve ESD robustness. The new ESD structure features tunable triggering voltage, low holding voltage, low on-impedance, low leakage (/spl sim/pA), fast response time (/spl sim/0.18 ns), and low parasitic effect. It can be placed under a bond pad and consumes little silicon. It passed 14 kV human body model and 15 kV air-gap International Electrotechnical Commission ESD zapping. It was demonstrated in commercial BiCMOS processes and is suitable for multiple-supply mixed-signal, parasitic-sensitive RF and high-pin-count ICs.

A single-crystal Si-resonator with on-chip readout amplifier in standard CMOS

The monolithic integration of electronic circuits in standard CMOS technology with high aspect ratio micromechanical structures based on single-crystal silicon is presented. For this technology neither silicon on insulator (SOI) wafers nor wet processes are required. A resonator device is chosen for technology demonstration. The effect of micromachining on parameters of CMOS transistors is detected and the usefulness of a final annealing step is confirmed. A novel electronic circuit design allows signal processing, even for low resonator signal levels and strong parasitic effects.

A novel on-chip electrostatic discharge protection design for RF ICs

A novel, compact electrostatic discharge (ESD) protection structure is designed, which protects integrated circuits (ICs) against ESD damages in all modes. This ultra-fast-response ESD structure, with response time of t1∼0.16nS, operates symmetrically. Measurements showed desired low holding voltage (∼2V), low discharging impedance (<2Ω), high current handling capacity and adjustable triggering voltages. ESD testing passed HBM 14 and 15kV air-gap IEC zapping. Design prediction was achieved by comprehensive mixed-mode ESD simulation. The area-efficient ESD design features small Si consumption, low parasitic effects and is particularly suitable for high-speed VLSI and RF ICs. The design was implemented in commercial sub micron BiCMOS technologies for multi-power-supplies mixed-signal ICs.

Packaging-compatible high Q microinductors and microfilters for wireless applications

To meet requirements in mobile communication and microwave integrated circuits, miniaturization of the inductive components that many of these systems require is of key importance. At present, active circuitry is used which simulates inductor performance and which has high Q-factor and inductance; however, such circuitry has higher power consumption and higher potential for noise injection than passive inductive components. An alternate approach is to fabricate integrated inductors, in which lithographic techniques are used to pattern an inductor directly on a substrate or a chip. However, integrated inductors can suffer from low Q-factor and high parasitic effects due to substrate proximity. To expand the range of applicability of integrated microinductors at high frequency, their electrical characteristics, especially quality factor, should be improved. In this work, integrated spiral microinductors suspended (approximately 60 /spl mu/m) above the substrate using surface micromachining techniques to reduce the undesirable effect of substrate proximity on the inductor performance are investigated. The fabricated inductors have inductances ranging from 15-40 nH and Q-factors ranging from 40-50 at frequencies of 0.9-2.5 GHz. Microfilters based on these inductors are also investigated by combining these inductors with integrated polymer filled composite capacitors.

Electroplated solder alloys for flip chip interconnections

Flip chip mounting of bare dice is gaining widespread use in microelectronics packaging. The main drivers for this technology are high packaging density, improved performance at high frequency, low parasitic effects and potentially high reliability and low cost. Many companies have made significant efforts to develop a technology for bump processing, bare die testing and underfill encapsulation to gain the benefit of all potential advantages. We have focussed on low cost bumping of fully processed silicon wafers to develop a flexible scheme for various reflow requirements. The bumping process is based on galvanic plating from an alloy solution or, alternatively, from several elemental plating baths. Sputtered Mo/Cu or Cr/Cu is used as a wettable base for electroplating. Excess base metal is removed by using the bumps as an etching mask. Variation of the alloy composition or the layer structure, allows the adjustment of the bump reflow temperature for the specific requirements of the assembly. Using binary tin-lead and ternary tin-lead-bismuth alloys, reflow temperatures from 100 °C (bismuth rich alloys) to above 300 °C (lead rich alloys) can be covered. The influence of the plating current density on the final alloy composition has been established by ion beam analysis of the plated layers and a series of reflow experiments. To control the plating uniformity and the alloy composition, a new cup plating system has been built with a random flow pattern and continuous adjustment of the current density. A well-controlled reflow of the bumps has been achieved in hot glycerol up to the eutectic point of tin-lead alloys. For high temperature alloys, high molecular weight organic liquids have been used. A tensile pull strength of 20 g per bump and resistance of 5 mΩ per bump have been measured for typical eutectic tin-lead bumps of 100 μm in diameter.

High-frequency performance limitations of millimeter-wave heterojunction bipolar transistors

Heterojunction bipolar transistor structure (HBTs) with 0.25-, 0.4-, and 0.6- mu m emitter stripe widths and ultrasubmicrometer base widths, which are designed to achieve minimum transit time and low parasitic effects, are examined for their millimeter-wave performance. In particular,the dependence of the unity current gain frequency (f/sub tau /), the maximum oscillation frequency (f/sub max/), and the stability of power gains on the device structure and material parameters are critically analyzed. It is shown that the classical f/sub max/ expression commonly used for bipolar transistors, involving the effective carrier transit time and the collector-based RC time constant does not adequately represent the performance of ultrasubmicrometer-based-width HBTs, where the transadmittance phase delay associated with the collector-base depletion layer transit time and the parasitic collector-based capacitance are significant. The expected ballistic and quasiballistic behaviour of electron in these ultrasubmicrometer structures, if properly designed, minimizes the effective carrier transit time effect, but its impact on the f/sub max/ by the excess transadmittance phase delay poses a more fundamental and serious high-frequency limiting factor for the realization of millimeter-wave HBTs than has been hitherto recognized. The accuracy and usefulness of the proposed analytical approach is demonstrated for a practical HBT structure with 1.2- mu m emitter stripe design, giving results that agree well with measurements. >