Low Oversampling Ratio Research Articles

Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers

As wideband Delta-Sigma-Modulators (DSMs) are restricted in oversampling ratio (OSR), and low OSR reduces the benefit of higher order loop filters, the increase of the internal resolution is an obvious way to achieve high signal-to-quantization-noise ratio (SQNR). State-of-the-art implementations restrict the internal resolution to mostly 4-6 bits, as efficient QTZs with higher resolution add excessive delay into the DSM. Multi-step or time-interleaved-quantizer (TI-QTZs) are an effective way to enhance resolution at high sampling rate, but the resulting latency in excess of one clock cycle usually prohibits their usage in DSMs. This paper proposes a new architecture to employ high resolution multi-step QTZs, such as TI SAR or pipeline ADCs. In the proposed architecture, an excess loop delay (ELD) of several clock cycles in the LSBs is purposefully allowed. While the MSBs are conventionally ELD-compensated, the LSBs are not. The resulting error is corrected in the digital domain. It is shown that matching requirements are relaxed by first-order shaping. The idea is also applicable to a Leslie-Singh and noise-coupling architecture, which are compared to the proposed architecture in an extensive system-level analysis and simulation. Depending on the target application, an advantageous design recommendation can be given based on the presented results depending on OSR, internal bitwidth and expected analog-digital matching.

Image Reconstruction for Low-Oversampled Staggered SAR via HDM-FISTA

Due to the unequispaced pulse repetition interval (PRI), the low-oversampling ratio and the range-variant blockage, the echo of the low-oversampled staggered SAR (LS-SAR) is nonuniformly sampled with sub-Nyquist and range-variant rate. However, the existing LS-SAR processing methods lack robustness with regards to the scenario type and the PRI variation mode. In this article, a compressive-sensing-based image reconstruction method for the LS-SAR is proposed. First, a hybrid-domain model (HDM) of the LS-SAR echo is presented. In the HDM, the coupled range cell migration (RCM), the unequispaced PRI, and the conflict blockage are formulated as the matrix multiplications with a 3-D tensor, a 2-D matrix, and a Hadamard product, respectively. Based on the HDM, the image reconstruction is realized through the 2-D fast iterative shrinkage thresholding algorithm (ISTA), in which the gradient is derived by exploiting the properties of the tensor and matrix trace. The fast Fourier transform (FFT) and the nonuniform FFT are implemented to accelerate the computation. Due to good accommodation of the RCM and the LS-SAR sampling characteristics, the proposed method can work well for various PRI variation modes and scenario types. Simulations using the point scatter and the distributed target with wide-swath extension demonstrate the effectiveness as well as the robustness of the proposed method.

A 400 mV 160 nW/Ch Compact Energy Efficient ∆Σ Modulator for Multichannel Biopotential Signal Acquisition System.

Analog to digitalconverter circuit design for biomedical systems with multiple recording channels presents challenges in high density and very low power consumption. Passive integrator and loop-filter based delta-sigma modulators (DSMs) have been recently reported for ultra-low-power and highly energy-efficient data converters for multi-channel biopotential acquisition. However, these modulators rely on a very high oversampling ratio (OSR) to achieve the target resolution. Higher OSR leads to higher power consumption in the modulator and the digital low-pass and decimation filter succeeding the DSM. We present a low OSR passive integrator-based DSM in this work by relying on a duty-cycled resistor (DCR). DCR enables the realization of large time constants in the already passive loop-filter, with minimal area and overhead power consumption. This leads to design of DSMs that are highly area, power and energy-efficient, suitable for multi-channel biopotential recording systems. We demonstrate a second order, duty-cycled passive integrator based CTDSM in a 65 nm CMOS technology for a 10 kHz biopotential bandwidth. Measurement results show that the fabricated design achieves an SNDR/DR of 56.36/63.1 dB while consuming only 160 nW power with an OSR of 32 and occupies an area of 0.035 mm 2 with a state-of-the-art energy efficiency of 14.9 fJ/conv. In-vitro and in-vivo measurements are provided to further demonstrate the operation of the proposed DSM.

Robust phase retrieval of complex-valued object in phase modulation by hybrid Wirtinger flow method

This paper presents a robust iterative algorithm, known as hybrid Wirtinger flow (HWF), for phase retrieval (PR) of complex objects from noisy diffraction intensities. Numerical simulations indicate that the HWF method consistently outperforms conventional PR methods in terms of both accuracy and convergence rate in multiple phase modulations. The proposed algorithm is also more robust to low oversampling ratios, loose constraints, and noisy environments. Furthermore, compared with traditional Wirtinger flow, sample complexity is largely reduced. It is expected that the proposed HWF method will find applications in the rapidly growing coherent diffractive imaging field for high-quality image reconstruction with multiple modulations, as well as other disciplines where PR is needed.

Resolution‐enhanced sturdy MASH delta–sigma modulator for wideband low‐voltage applications

A resolution-enhanced sturdy multi-stage noise shaping (MASH) delta–sigma modulator is presented. By employing the Leslie-Singh architecture in the first stage and an appropriate second stage digital filtering, the proposed structure could achieve much higher resolution [>80 dB signal-to-quantisation noise ratio] when compared with a traditional sturdy MASH, at a lower oversampling ratio (e.g. 8X). Interestingly, the mismatch between digital and analogue transfer functions is inherently shaped so that the structure is not sensitive to opamp finite gain error. Both these properties make the proposed structure suitable for wideband low-voltage applications. Behavioural simulations are presented to demonstrate the effectiveness of the proposed structure when compared with the prior art of its high performance delta–sigma counterparts.

High‐loop‐delay sixth‐order bandpass continuous‐time sigma–delta modulators

This study focuses on the design of high-loop-delay modulators for parallel sigma-delta conversion. Parallel converters, allowing a global low oversampling ratio, consist of several bandpass modulators with adjacent central frequencies. To ensure the global performance, the noise transfer function (NTF) of each modulator must be adjusted regarding its central frequency. In this thematic a new topology of sixth-order modulators based on weighted-feedforward techniques is developed. This topology offers an adequate control of the NTF at each central frequency by simple means. Additive signal paths are moreover proposed to obtain an auto-filtering signal transfer function. An optimisation method is also developed to calculate the optimised coefficients of the modulators at different central frequencies. The main concerns are improving the stability and reducing the sensitivity of the continuous-time circuit to analogue imperfections. This is essential for parallel conversion since, in each channel, the modulator works at a central frequency which differs from the fourth of the sampling frequency. The performance of the optimised modulator is compared with its discrete-time counterpart with good argument.

High-Order Multibit Modulators and Pseudo Data-Weighted-Averaging in Low-Oversampling>tex<$Delta Sigma$>/tex<ADCs for Broad-Band Applications

High-speed high-resolution /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR). However, lowering the OSR limits the efficiency of a /spl Delta//spl Sigma/ ADC in achieving a high-resolution A/D conversion. This paper presents several techniques that enable the OSR reduction in /spl Delta//spl Sigma/ ADCs without compromising the resolution. 1) Noise transfer function (NTF). In this paper, a single-stage multibit /spl Delta//spl Sigma/ modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs. Its key features include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities. Its performance is validated through behavioral simulations and compared to traditional /spl Delta//spl Sigma/ modulator structures. 2) Signal transfer function (STF). This paper describes how the STF of a /spl Delta//spl Sigma/ modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation. 3) Dynamic element matching (DEM) is also presented. Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit /spl Delta//spl Sigma/ modulator, especially when the number of DAC elements is large. However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range. This paper proposes a simple technique, called pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio. Its implementation adds no extra delay in the /spl Delta//spl Sigma/ feedback loop and requires only minimal additional digital hardware. Existing schemes for DWA tone reduction are also compared.

Biasing technique for high dynamic range, low oversampling ratio continuous-time ΣΔ modulators without calibration

An accurate, continuous-time, active IC filter based on Gm-C integrators dedicated to the design of high dynamic range, low-oversampling ratio (OSR) continuous-time (CT) sigma-delta (ΣΔ) modulators is presented. Despite temperature and process variations, the biasing technique used enables design of a constant Gm-C cell without additional tuning circuit. A zero-IF (ZIF) receiver has been designed integrating I (in-phase) and Q (quadrature-phase) ΣΔ modulators. The measured peak SNR for a single modulator is 82.5 dB in temperature range [−30°C, +85°C]. Its power consumption, including I and Q modulators, biasing circuitry and delay-locked loop is 7.25 mW under 2.5 V.

A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass /spl Delta//spl Sigma/ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-/spl mu/m CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz.

A wideband CMOS sigma-delta modulator with incremental data weighted averaging

A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-/spl mu/m CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dissipation is less than 105 mW and the active area is 2.6 mm/sup 2/. Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance.

A new design and performance -test strategy for sigma-delta modulators

The paper proposes a new approach to sigma-delta modulator design based on linear and non-linear control theories combined with a number of digital signal processing techniques. The limitations single-stage high-order designs are analysed as a compatibility problem between the linear filtering and non-linear quantiser requirements. The comnplexity versus performance-improvements of other strategies are also discussed. In addition to the new approach to component-compatibility analysis, the paper proposes a more rigorous analyses of the system performance by using, for the first time, groups of harmonic-rich test signals. Based on this new approach and the extensive analysis of how jointly and severally the linear and non-linear parameters influence the modulator's performance, a new design strategy is proposed and results demonstrated on a single-stage second-order modulator. The results are compared with those of an already-published second-order design for low over-sampling ratio of 64. It is shown that under the same conditions the new modulator exhibits a significantly improved signial-to-noise-ratio response' over a wide dynamic range of input signals. Finally, the conclusion discusses how this approach can be extendecl to other designs as well as used as a framework to completeyl new adaptive strategies.