Low Memory Bandwidth Research Articles

Implementation of Boneh - Lynn - Shacham short digital signature scheme using Weil bilinear pairing based on supersingular elliptic curves

One option for a digital signature solution for devices with low memory and low bandwidth transmission over channels uses a short digital signature scheme based on Weil bilinear pairing aimed at short processing times, fast computation, and convenient deployment on applications. The computational technique of non-degenerate bilinear pairings uses supersingular elliptic curves over a finite field Fpl (where p is a sufficiently large prime number) and has the advantage of being able to avoid Weil-descent, Menezes-Okamoto-Vanstone (MOV) attacks, and attacks by the Number Field Sieve algorithm. Compared to Elliptic Curve Digital Signature Algorithm (ECDSA) digital signature schemes, generating a digital signature for a Boneh-Lynn-Shacham (BLS) scheme using Weil bilinear pairing on a supersingular elliptic curve is simple. In this study, the authors replace non-degenerate bilinear pairing calculations on a supersingular elliptic curve with a Weil pairing with PεE(Fp ), QεE(Fp1) and a higher security multiplier α=12 in the BLS short digital signature scheme. The execution time of the BLS short digital signature program showed improvement compared to the commercial ECDSA digital signature scheme.

Parallelization and Optimization of NSGA-II on Sunway TaihuLight System

Sunway TaihuLight system is the first supercomputer offering a peak performance over 100 PFlops, which can be utilized to parallelize Non-dominated Sorting Genetic Algorithm II (NSGA-II), a standard approach to multi-objective optimization. However, insufficient off-chip memory bandwidth and limited scratchpad memory capacity of the supercomputer hinder the performance improvement of parallellizing NSGA-II. In this article, we propose an optimized parallel NSGA-II on Sunway TaihuLight system, called swNSGA-II, by utilizing process- and thread-level parallelism of the system based on an improved island/master-slave model. To overcome the hurdles of low memory bandwidth and capacity, we propose a data sharing scheme based on register-level communication that can efficiently parallelize non-dominated sorting and crowding-distance computation of NSGA-II. Several optimization techniques including vectorization, direct memory accessing, and double buffering are also adopted to further accelerate swNSGA-II. Experiment results show that the proposed swNSGA-II can achieve a speedup of 41284 on a use case of path planning, and a speedup of 62692 on ZDT1 as compared to conventional NSGA-II.

Toward a Microarchitecture for Efficient Execution of Irregular Applications

Given the increasing importance of efficient data-intensive computing, we find that modern processor designs are not well suited to the irregular memory access patterns often found in these algorithms. Applications and algorithms that do not exhibit spatial and temporal memory request locality induce high latency and low memory bandwidth due to the high cache miss rate. In response to the performance penalties inherently present in applications with irregular memory accesses, we introduce a GoblinCore-64 (GC64) architecture and a unique memory hierarchy that are explicitly designed to exploit memory performance from irregular memory access patterns. GC64 provides a pressure-driven hardware-managed concurrency control to minimize pipeline stalls and lower the latency of context switches. A novel memory coalescing model is also introduced to enhance the performance of memory systems via request aggregations. We have evaluated the performance benefits of our approach using a series of 24 benchmarks and the results show nearly 50% memory request reductions and a performance acceleration of up to 14.6×.

Implementation and performance of Barnes-hut n-body algorithm on extreme-scale heterogeneous many-core architectures

In this paper, we report the implementation and measured performance of our extreme-scale whole planetary ring simulation code on Sunway TaihuLight and two PEZY-SC2 systems: Shoubu System B and Gyoukou. The numerical algorithm is the parallel Barnes-Hut tree algorithm, which has been used in many large-scale astrophysical particle-based simulations. Our implementation is based on our FDPS framework. However, the extremely large numbers of cores of the systems used (10 M on TaihuLight and 16 M on Gyoukou) and their relatively poor memory and network bandwidth pose new challenges. We describe the new algorithms introduced to achieve high efficiency on machines with low memory bandwidth. The measured performance is 47.9, 10.6 PF, and 1.01PF on TaihuLight, Gyoukou and Shoubu System B (efficiency 40%, 23.5% and 35.5%). The current code is developed for the simulation of planetary rings, but most of the new algorithms are useful for other simulations, and are now available in the FDPS framework.

Performance Measure Modeling of Routing Protocols in MANET

Mobile ad-hoc networks (MANETs) are recently attracting a lot of interest due to their widely available wireless devices and low communication cost. MANET comprises a set of wireless communicating devices able to connect instantaneously without any preexisting base station. Due to a limited transmission range of mobile devices, they need multi-hop routing for communication. In MANET nodes can change topology in an unpredictable manner so they need an efficient routing protocol which can handle the changing topology. However, MANET suffers from many challenges, including decentralization, low memory device, infrastructure less, bandwidth and limited battery reservoir. Different modes of the nodes like active-communication mode and non-activecommunication mode consume available energy of a node. This paper presents an energy measurement model which shows the remaining energy level in each mobile node after some activity. The parameters required for designing energy measurement model consist of initialEnergy, txPower, rxPower, and idlePower. This paper also evaluates the performance measure metrics of two routing protocols such as Ad hoc On Demand Distance Vector (AODV) and Destination Sequenced Distance Vector (DSDV). This paper analyzes these routing protocols by simulation tested in network simulator (NS2). The performance will be studied based on Throughput, Packet loss, Routing delay, Cumulative sum of dropped packets, Calculate energy consumption and remaining energy at each node.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm2 integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm2 chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

Frame Rate Up-Conversion Method for Video Processing Applications

In this paper, a new low-complexity frame rate up-conversion (FRUC) method is proposed for video processing applications. In the proposed FRUC method, true motion estimation (TME) is used to track motion trajectories by imposing smoothness constraints on block-matching algorithm (BMA). In order to produce high-quality interpolated frames, TME is performed in both forward and backward directions; then, the reliable dense motion vector field is obtained by using the multistage motion vector (MV) post-processing method. The constraints of low computational complexity and low memory bandwidth are also considered in our method. We use a histogram-based predictive search to impose smoothness constrains and reduce the number of search points. Furthermore, a complexity-simplified improvement of the proposed method is introduced to reduce computational complexity with slight quality degradation. In addition, a new scan order of BMA and a pipelining of MV post-processing are presented to guarantee the causality of the system and improve the pixel data reuse, which reduces the memory bandwidth. The experiment results show that the proposed FRUC method achieves not only better video quality, but also low computational complexity and memory bandwidth compared to the conventional methods.

Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement

Montgomery modular multiplication is widely used in public-key cryptosystems. This work shows how to relax the data dependency in conventional word-based algorithms to maximize the possibility of reusing the current words of variables. With the greatly relaxed data dependency, we then proposed a novel scheduling scheme to alleviate the number of memory access in the developed scalable architecture. Analytical results show that the memory bandwidth requirement of the proposed scalable architecture is almost 1/(w - 1) times that of conventional scalable architectures, where w denotes word size. The proposed one also retains a latency of exactly one cycle between the operations of the same words in two consecutive iterations of the Montgomery modular multiplication algorithm when employing enough processing elements. Compared to the design in the related work, experimental results demonstrate that the proposed one achieves an almost 54 percent reduction in power consumption with no degradation in throughput. The reduced number of memory access not only leads to lower power consumption, but also facilitates the design of scalable architectures for any precision of operands.

Robust real-time pedestrians detection in urban environments with low-resolution cameras

Detecting that pedestrians are present in front of a vehicle is highly desirable to avoid dangerous traffic situations. A novel vision-based system is presented to automatically detect far-away pedestrians with low-resolution cameras mounted in vehicles given the contributions of fixed cameras present in the scene.Fixed cameras detect pedestrians by solving an inverse problem built upon a multi-class dictionary of atoms approximating the foreground silhouettes. A sparse-sensing strategy is proposed to extract the foreground silhouettes and classify them in real-time. Mobile cameras detect pedestrians given only their appearance in the fixed cameras. A cascade of compact binary strings is presented to model the appearance of pedestrians and match them across cameras.The proposed system addresses the practical requirements of transportation systems: it runs in real-time with low memory loads and bandwidth consumption. We evaluate the performance of our system when extracted features are severely degraded and the sensing devices are of low quality. Experimental results demonstrate the feasibility of our collaborative vision-based system.

묵시적 가중 예측기법을 이용한 저 메모리 대역폭 인터 예측기 설계

본 논문에서는 H.264/AVC 인코더의 성능 향상을 위해 다중 참조 프레임 기법과 묵시적 가중 예측 기법을 이용하고 낮은 외부 메모리 접근율을 위해 이전 참조 프레임 데이터를 재사용하는 인터 예측기 하드웨어 구조를 제안한다. 참조 소프트웨어JM16.0과 비교하여 참조 프레임 접근율이 약 24%만큼 감소하고 참조 영역 메모리가 약 46%만큼 감소하였다. 통합 구조는 Verilog HDL로 설계되고 Magnachip 0.18um공정으로 합성한 결과 게이트 수는 약 2,061k 이고 91Mhz로 동작한다. In this paper, for improving the H.264/AVC hardware performance, we propose an inter predictor hardware design using a multi reference frame selector and an implicit weighted predictor. previous reference frame are reused for Low Memory Bandwidth. The size of the reference memory in the predictor was reduced by about 46% and the external memory access rate was reduced by about 24% compared with the one in the reference software JM16.0. We designed the proposed system with Verilog-HDL and synthesized inter predictor circuit using the Magnachip 0.18um CMOS standard cell library. The synthesis result shows that the gate count is about 2,061k and the design can run at 91MHz.

Performance Evaluation and Optimization on GPU

GPU provides higher peak performance with hundreds of cores than CPU counterpart. However, it is a big challenge to take full advantage of their computing power. In order to understand performance bottlenecks of applications on many-core GPU and then optimize parallel programs on GPU architectures, we propose a performance evaluating model based on memory wall and then classify applications into AbM (Application bound-in Memory) and AbC (Application bound-in Computing). Furthermore, we optimize kernels characterized with low memory bandwidth including matrix multiplication and FFT (Fast Fourier Transform) by employing texture cache on NVIDIA GTX280 using CUDA (Compute Unified Device Architecture). Experimental results show that texture cache is helpful for AbM with better data locality, so it is critical to utilize GPU memory hierarchy efficiently for performance improvement.

LEVERAGING SHARED CACHES FOR PARALLEL TEMPORAL BLOCKING OF STENCIL CODES ON MULTICORE PROCESSORS AND CLUSTERS

Bandwidth-starved multicore chips have become ubiquitous. It is well known that the performance of stencil codes can be improved by temporal blocking, lessening the pressure on the memory interface. We introduce a new pipelined approach that makes explicit use of shared caches in multicore environments and minimizes synchronization and boundary overhead. Benchmark results are presented for three current x86-based microprocessors, showing clearly that our optimization works best on designs with high-speed shared caches and low memory bandwidth per core. We furthermore demonstrate that simple bandwidth-based performance models are inaccurate for this kind of algorithm and employ a more elaborate, synthetic modeling procedure. Finally we show that temporal blocking can be employed successfully in a hybrid shared/distributed-memory environment, albeit with limited benefit at strong scaling.

A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration

Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 m fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output.

Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension

In addition to coding efficiency, the scalable extension of H.264/AVC provides good functionality for the adaptation in heterogeneous environments. Fine grain scalability (FGS) is a technique to extract video at the best quality level under the available bandwidth. In this paper, an architecture of FGS encoder with low external memory bandwidth and low hardware costs is developed. At most 92% bandwidth reduction can be attained by the proposed scan bucket algorithm, early context modeling with context reduction, and first scan pre-encoding. The area-efficient architecture is implemented by layer-wise hardware reuse, and three design strategies for enhancement layer coder are explored so that the trade-off between external memory bandwidth and silicon area is allowed. This design can real-time encode HDTV 1280×720 video at 130 MHz working frequency.

High-Quality Mipmapping Texture Compression With Alpha Maps for Graphics Processing Units

Texture compression is an important technique in graphics processing units (GPUs) for saving memory bandwidth. This paper presents a high-quality mipmapping texture compression (MTC) system with alpha maps. Based upon the wavelet transform, a hierarchical approach is adopted for mipmapping textures in the YCbCr color space and alpha channel. By inspecting the similarity between the alpha and luminance channels, the two channels are efficiently encoded together with linear prediction in the differential mode. In addition, the split mode manages textures with no strong relationship between the alpha and luminance channels. A layer overlapping technique is also proposed to reduce the texture memory bandwidth. Simulation results show that MTC can reduce the texture access traffic by 80% to 90% and provides high image quality as well. Compared with DirectX texture compression (DXTC), the most well-known texture compression with alpha maps, MTC reduces the texture access bandwidth by 30% more. VLSI implementation results show that the hardware cost of MTC is similar to that of DXTC and that MTC is suitable for integration in GPUs to provide high-quality textures with low memory bandwidth requirements.

An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems

The implementation of the memory for storing image and transform coefficients in 2-D DWT processing systems using the more cost-effective external memory module such as DDR DRAM is shown to suffer from effective memory bandwidth which is significantly lower than the memory system peak bandwidth if the conventional direct logical-to-physical memory address mapping is adopted. The low effective memory bandwidth is caused by the high level of memory overhead cycle occurrence which is in turn is closely related to the logical memory access patterns of 2-D DWT processes. The problem becomes even more severe for the 2-D DWT processing of video. An analysis on the logical memory access patterns of multi-level 2-D DWT is carried out and an enhanced logical-to-physical memory mapping scheme which minimizes the occurrence of memory overhead cycles is proposed. The proposed scheme is simulated and its performance in terms of effective memory access bandwidth is evaluated and compared with the conventional direct mapping scheme.

A high throughput 3D-bus interconnect for network processors

Deep layer processing and increasing line rates present a memory challenge to processor–memory communications located on network line cards. In this paper, we introduce a packet-based, off-chip interconnect to increase the throughput of memory system currently used on line cards. The 3D-bus architecture allows multiple packet processing elements on a line card to access multiple memory modules. Our network-on-board includes a routing protocol as well as a node switching mechanism to minimize packet congestion and packet loss. The main advantage of the proposed architecture is to increase the network processor off-chip memory bandwidth while diminishing the latency otherwise caused by the single bus competition. Performance results show that our interconnect significantly outperforms its competitors, such as shared-bus, PCI Express, infiniband and HyperTransport, reaching peak throughput beyond 400 Gbps. Moreover, it provides other high performance qualities including low latency, off-chip scalability, low transmission failure-rate and high memory bandwidth.

A novel all-binary motion estimation (ABME) with optimized hardware architectures

We present a fast motion estimation algorithm using only binary representation, which is desirable for both embedded system and hardware implementation with parallel architectures. The key algorithm distinction is that only the high-frequency spectrum is used. Our experimental results show that it provides excellent performance at both low and high bit rates. Because of its binary-only representation, the proposed algorithm offers low computational complexity and low memory bandwidth consumption. For multimedia-embedded system design, we further investigated specific implementation techniques for several well-known hardware platforms including Intel x86 processors, single-instruction multiple-data processors, and systolic array circuit design. The systolic array architecture requires only single memory access for both the reference and current frames from the on-chip memory. Such an implementation provides an optimized solution with great throughput, while the quality is maintained. Finally, we show that our binarization methods are closely coupled to the accuracy of binary motion estimation algorithms. The binarization and coding efficiencies can be improved using various filters and binarization methods.

High-throughput block-matching VLSI architecture with low memory bandwidth

A full-search block-matching architecture which features high throughput, low data input lines, and low memory bandwidth is proposed. It reduces memory I/O requirements by the maximum reuse of search data using on-chip memory. It also promises a high throughput rate by the continuous calculation of all block distortions in a search area using two search data input flows without processing any invalid block distortion, and by the continuous process of the neighbored reference blocks removing the initialization period between blocks. The processor for -16/+15 search ranges, implemented in the total 220 k gates using 0.6 /spl mu/m triple-metal CMOS technology, can operate at a 66 MHz clock rate, and therefore is capable of encoding H.263(4CIF), MPEG2(MP@ML), and other multimedia applications.

A novel video signal processor with programmable data arrangement and efficient memory configuration

This paper describes a novel video signal processor (VSP) with a fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of a programmable data arrangement and an intelligent memory configuration. Techniques for reducing the interconnections and external memory accesses are also presented. A configuration of random-access on-chip memory modules solves the problems of chip I/O and memory bandwidth requirement. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications.