Low Input-referred Noise Research Articles

High-precision high-speed nanopore ping-pong control system based on field programmable gate array.

"Molecular ping-pong," emerging as a control strategy in solid-state nanopore technology, presents a highly promising approach for repetitive measurements of single biomolecules, such as DNA. This paper introduces a high-precision, high-speed nanopore molecular ping-pong control system consisting of a home-built trans-impedance amplifier (TIA), a control system based on a Field Programmable Gate Array (FPGA), and a LabVIEW program operating on the host personal computer. Through feedback compensation and post-stage boosting, the TIA achieves a high bandwidth of about 200kHz with a gain of 100 MΩ, along with low input-referred current noise of 1.6 × 10-4pA2/Hz at 1kHz and 1.1 × 10-3pA2/Hz at 100kHz. The FPGA-based control system demonstrates a minimum overall response time (tdelay) of 6.5 μs from the analog input current signal trigger to the subsequent reversal of the analog output drive voltage signal, with a control precision of 1 μs. Additionally, a LabVIEW program has been developed to facilitate rapid data exchange and communication with the FPGA program, enabling real-time signal monitoring, parameter adjustment, and data storage. Successful recapture of individual DNA molecules at various tdelay, resulting in an improvement in capture rate by up to 2 orders of magnitude, has been demonstrated. With unprecedented control precision and capture efficiency, this system provides robust technical support and opens novel research avenues for nanopore single-molecule sensing and manipulation.

A 382nVrms 100GΩ@50Hz Active Electrode for Dry-Electrode EEG Recording.

This article describes a low noise and ultra-high input impedance active electrode (AE) interface chip for dry-electrode EEG recording. To compensate the input parasitic capacitance and the ESD leakage, power/ground/ESD bootstrapping is proposed. This design integrates chopping stabilization technique to suppress flicker noise of the amplifier which has never been tackled in previous bootstrapped AE design. Both on-chip and off-chip input routing is active shielded to minimize wire parasitic. Fabricated in a 0.18μm CMOS process, the AE core occupies about 0.056mm2 and draws 17.95μA from a 1.8V supply. The proposed AE achieves 100GΩ input impedance at 50Hz and over 1GΩ at 1kHz with a low input-referred noise of 382nVrms integrated from 0.5Hz to 70Hz. This design is the first 100GΩ@50Hz input impedance chopper stabilized AE compared to the state-of-the-art. Dry-electrode EEG recording capability of the proposed AE are verified on three types of experiments including spontaneous α-wave, event related potential and steady-state visual evoked potential.

A Low-Noise Low-Power 0.001Hz-1kHz Neural Recording System-on-Chip With Sample-Level Duty-Cycling.

Advances in brain-machine interfaces and wearable biomedical sensors for healthcare and human-computer interactions call for precision electrophysiology to resolve a variety of biopotential signals across the body that cover a wide range of frequencies, from the mHz-range electrogastrogram (EGG) to the kHz-range electroneurogram (ENG). Existing integrated wearable solutions for minimally invasive biopotential recordings are limited in detection range and accuracy due to trade-offs in bandwidth, noise, input impedance, and power consumption. This article presents a 16-channel wide-band ultra-low-noise neural recording system-on-chip (SoC) fabricated in 65nm CMOS for chronic use in mobile healthcare settings that spans a bandwidth of 0.001 Hz to 1 kHz through a featured sample-level duty-cycling (SLDC) mode. Each recording channel is implemented by a delta-sigma analog-to-digital converter (ADC) achieving 1.0 μ V rms input-referred noise over 1Hz-1kHz bandwidth with a Noise Efficiency Factor (NEF) of 2.93 in continuous operation mode. In SLDC mode, the power supply is duty-cycled while maintaining consistently low input-referred noise levels at ultra-low frequencies (1.1 μV rms over 0.001Hz-1Hz) and 435 M Ω input impedance. The functionalities of the proposed SoC are validated with two human electrophysiology applications: recording low-amplitude electroencephalogram (EEG) through electrodes fixated on the forehead to monitor brain waves, and ultra-slow-wave electrogastrogram (EGG) through electrodes fixated on the abdomen to monitor digestion.

A Voltage-Assist 16-Channel Electrochemical Biosensor with Linearity Compensation.

Large capacitive loading of electrodes induces massive error current and imperfect settling in the electrochemical signal acquisition process, leading to inaccurate acquisition results. To efficiently mitigate this inaccuracy, this paper presents a current-and-voltage dual-mode acquisition technique in which a voltage front-end (VFE) is employed to acquire the electrode voltage error and compensate the nonlinearity induced by the electrode capacitive loading. Therefore, the gain and bandwidth requirements of the current front end (CFE) can be relaxed to reduce the complexity and power consumption. With a relieved gain requirement, an inverter-based capacitive trans-impedance amplifier (IB-CTIA) is adopted to boost the input transconductance for low-noise design. By reusing the supply current, the IB-CTIA effectively achieves a low input-referred current noise of 3.9 pArms and a dynamic range (DR) of 126 dB with only 18-μW static power. The prototype chip is fabricated in a 180-nm CMOS process. Interleukin-6 immunoassays (IL-6) are implemented to verify the chip's performance. With the proposed nonlinear error compensation, the correlation coefficient of the detection result is improved from 0.951 to 0.980 and the limit of detection (LoD) is reduced from 8.31 pg/mL to 6.90 pg/mL.

Design of a Configurable 4-Channel Analog Front-End for EEG Signal Acquisition on 180nm CMOS Process

In this work, a 4-channel Analog Front-End (AFE) circuit has been proposed for EEG signal recording. For EEG recording systems, the AFE may handle a wide range of sensor inputs with high input impedance, adjustable gain, low noise, and wide bandwidth. The buffer or current-to-voltage converter block (BCV), which can be set to operate as a buffer or a current-to-voltage converter circuit, is positioned between the electrode and the main amplifier stages of the AFE to achieve high input impedance and work with sensor signal types. A chopper capacitively-coupled instrumentation amplifier (CCIA) is positioned after the BCV as the main amplifier stage of the AFE to reduce input-referred noise and balance the impedance of the overall AFE system. A programmable gain amplifier (PGA) is the third stage of the AFE that allows the overall gain of the AFE to be adjusted. The suggested AFE operates in a wide frequency range of 0.5 Hz to 2 kHz with a high input impedance bigger than 2TΩ, and it is constructed and simulated using a 180nm CMOS process. With the lowest 100-dB CMRR and low input-referred noise of 1.8 µVrms, the AFE can achieve low noise efficiency. EEG signals can be acquired with this AFE system, which is very useful for detecting epilepsy and seizures.

Design of ECG circuits for wearable devices

Heart diseases have become more and more prominent in recent years. ECG signals can accurately reflect the health of hearts during the detection process. The use of wearable ECG devices requires low power consumption, a high common-mode rejection ratio, and minimal noise. Traditional research has concentrated on lowering the circuit's overall power dissipation, which typically results in less current flowing through the amplifier but higher circuit noise. Therefore, this places higher demands on the amplifier in the circuit. Electronic devices are becoming smaller due to the rapid development of semiconductor technology. Amplifiers designed for semiconductor devices can effectively solve the problems mentioned above. The circuit created in this study has a low power need, a high common-mode rejection ratio, is compact, has a high input impedance, and has a low input-referred noise level. In addition, LT-Spice software was used to design and simulate the circuit, and the results were analyzed and calculated accordingly. The circuit meets the requirements of the project design. The frequency range of the circuit is 1mHz - 227.9Hz. The differential gain of the circuit is 36.6dB. The integrated input-fred noise is 3.94uV. The total consumption of electricity is 4.67W. These data indicate that the circuit has a high gain in the frequency range of ECG signals, which can filter out other interference signals. It also solves the problems of power consumption and noise.

A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation

This brief proposes a fully dynamic discrete-time (DT) Σ ADC using a correlated level shifting (CLS)-assisted floating inverter amplifier (FIA) with a sampling noise cancellation (SNC) technique. The CLS-assisted FIA improves amplifier gain with a single-stage configuration, which has lower input-referred noise than the cascaded one. In combination with the proposed SNC, the noise contribution of the 1st-stage integrator can be minimized. We also propose a novel passive integrator cascaded with a passive adder that avoids unwanted inter-stage loading without a speed penalty. The prototype of the proposed ADC fabricated in a 65 nm bulk CMOS process realizes a fully dynamic operation and achieves 94.8 dB SNDR with an OSR of 256 for 19.5 kHz bandwidth while consuming 79.2 W from a 1.2V supply at a 10 MHz sampling frequency. The Schreier and Walden FoMs are respectively 178.7 dB and 45.2 fJ/conv.-step, which are the best among recent fully dynamic DT Σ ADCs with similar bandwidth.

Design of a 1.8-µVrms IRN 180-dB CMRR configurable low-noise 6-channel analog front-end for neural recording systems on 180nm CMOS process

This paper presents a configurable analog front-end (AFE) for low-power neural recording systems that is capable of the current-to-voltage converter, programmable gain, ultra-high input impedance, low-noise, and wide bandwidth. A 6-channel AFE consisting of 6 1-channel AFEs is also introduced in this paper. The proposed AFE is designed on a 180nm CMOS process for low noise and operates over a wide frequency range of 0.5 Hz to 2.3 kHz with low input-referred noise of 1.8 μVrms and the maximal CMRR value of 180 dB. The power consumption is 8.5 μW per channel.

A Micropower Chopper CBIA with DSL-Embedded Input Stage with 0.4 V EO Tolerance for Dry-Electrode Biopotential Recording.

A chopper instrumentation amplifier (IA) dedicated for bio-potential acquisition usually requires a linearized input stage for large electrode offset voltage accommodation. This linearization leads to excessive power consumption when sufficiently low input-referred noise (IRN) is required. We present a current-balance IA (CBIA) without the need for the input stage linearization. It uses two transistors to operate as an input transconductance stage and a dc-servo loop (DSL) at the same time. An off-chip capacitor completes the DSL by ac coupling the source terminals of the input transistors via chopping switches realizing a sub-Hz high-pass cutoff frequency for dc rejection. Fabricated in a 0.35-μm CMOS process, the proposed CBIA occupies 0.41 mm2 and consumes 1.19 μW from a 3 V dc supply. Measurements show that the IA achieves an input-referred noise of 0.91 μVrms over 100 Hz bandwidth. This corresponds to a noise efficiency factor of 2.22. Typical CMRR of 102.1 dB is achieved for zero offset and degraded to 85.9 dB when a ±0.3 V input offset was applied. Gain variation of 0.5% is maintained within the range of ±0.4V input offset. The resulting performance meets well with the requirement for ECG and EEG recording using dry electrodes. A demonstration for the use of the proposed IA on a human subject is also provided.

Design and Simulation of Low Power Differential Transimpedance Amplifier Using Degenerations Capacitors

In today’s internet-connected culture, high-speed data transmission techniques are in high demand. Optical communication is most used techniques for data transmission with speed. High-speed amplifiers are needed, nevertheless, to obtain high gains and transform current signals into voltage gains. This is accomplished via transimpedance amplifiers, a crucial component of optical receivers. In this work, a high-speed transimpedance amplifier with negative degeneration capacitors and complete differential operation is built. The proposed design has a transimpedance gain of approximately 52.4 dB at 19.8 GHz and an average input-referred noise current of roughly 23.3 pA/√Hz. The suggested circuit also has an high gain, and low input-referred noise, excellent bandwidth all of which contribute to its low power consumption of roughly 215 uW. This makes it appropriate for Internet of Things (IoT) devices, smart devices, mobile phones, laptops, and other computer peripherals.

Wearable Fetal ECG Monitoring System from Abdominal Electrocardiography Recording.

Fetal electrocardiography (ECG) monitoring during pregnancy can provide crucial information for assessing the fetus’s health status and making timely decisions. This paper proposes a portable ECG monitoring system to record the abdominal ECG (AECG) of the pregnant woman, comprising both maternal ECG (MECG) and fetal ECG (FECG), which could be applied to fetal heart rate (FHR) monitoring at the home setting. The ECG monitoring system is based on data acquisition circuits, data transmission module, and signal analysis platform, which consists of low input-referred noise, high input impedance, and high resolution. The combination of the adaptive dual threshold (ADT) and the independent component analysis (ICA) algorithm is employed to extract the FECG from the AECG signals. To validate the performance of the proposed system, AECG is recorded and analyzed of pregnant women in three different postures (supine, seated, and standing). The result shows that the proposed system can record the AECG in different postures with good signal quality and high accuracy in fetal ECG and heart rate information. Sensitivity (Se), positive predictive accuracy (PPV), accuracy (ACC), and their harmonic mean (F1) are utilized as the metrics to evaluate the performance of the fetal QRS (fQRS) complexes extraction. The average Se, PPV, ACC, and F1 score are 99.62%, 97.90%, 97.40%, and 98.66% for the fQRS complexes extraction,, respectively. This paper shows the proposed system has a promising application in fetal health monitoring.

A strip line technique based 1 Gb/s, 70-dB linear dynamic range transimpedance amplifier towards LiDAR unmanned vehicle application

1This work reports a Microstrip Line (MSL) based Dual-Gate MOSFET (DGMOSFET) Transimpedance amplifier (TIA) for LIDAR unmanned vehicle application under different weather conditions. TIA (Design-I) is proposed under normal weather, while TIA (Design-II) for foggy weather conditions. TIA (Design-I) employs a variable gain common gate topology with post-amplification, resulting in high gain, wide bandwidth, and high dynamic range (DR). TIA (Design-II) incorporates a series MSL section at the input of TIA (Design-I), which further enhances the bandwidth performance. TIA (Design-I) realizes a fractional bandwidth of 104.3% with a transimpedance gain of 100.4 dBΩ and low input-referred noise (IRN) density of 4.29 pA/√Hz. TIA (Design-II) achieves a fractional bandwidth of 178.4% with transimpedance gain, IRN, and DR of 100.42 dBΩ, 3.81 pA/√Hz, and 70 dB, respectively. TIA (Design-II) demonstrates a 1 Gb/s data rate with a bit-error-rate < 10−10. The TIA (Design-I) and TIA (Design-II) consume the power of 33 mW and 39 mW under the supply voltage of 2 V.

Transconductance Boosting Technique for Bandwidth Extension in Low-Voltage and Low-Noise Optical TIAs

This paper presents a TIA topology with an active feedback path and a current bleeding circuit to relax the tradeoffs among gain, bandwidth and headroom limitations in a low voltage design. Using a two-stage common-source amplifier in the feedback path creates adequate degrees-of-freedom in the design for lowering the input resistance of the TIA and improving the bandwidth without degrading the amplifier gain. Analysis of the TIA transfer function and noise provide design guidelines for a well-behaved time response and low input-referred current noise. To demonstrate efficiency of the proposed technique, two designs in 0.18 μm CMOS technology with different values of the input capacitor are presented. The comparison of the designs with two categories of TIAs reported in the literature validates effectiveness of the presented transconductance boosting technique and demonstrates the flexibility of the proposed topology for different applications with a vast variety of the capacitance values at the TIA input.

Homemade-HEMT-based transimpedance amplifier for high-resolution shot-noise measurements.

We report a cryogenic transimpedance amplifier (TA) suitable for cross-correlation current-noise measurements. The TA comprises homemade high-electron-mobility transistors with high transconductance and low noise characteristics, fabricated in an AlGaAs/GaAs heterostructure. The low input-referred noise and wide frequency band of the TA lead to a high resolution in current-noise measurements. The TA's low input impedance suppresses unwanted crosstalk between two distinct currents from a sample, justifying the advantage of the TA for cross-correlation measurements. We demonstrate the high resolution of a TA-based experimental setup by measuring the shot noise generated at a quantum pointcontact in a quantum Hall system.

Improved Correlated Multiple Sampling by Using Interleaved Pixel Source Follower for High-Resolution and High-Framerate CMOS Image Sensor

This article describes an improvement in the noise reduction performance of a column correlated multiple sampling (CMS) readout circuit using interleaved pixel source follower for high-resolution and high-framerate CMOS image sensors (CISs). In this architecture, the time-interleaved operation of the two pixel source followers reduces the restrictions imposed by the settling time of the pixel source followers and extends the time for multiple sampling. The noise analysis indicates that this method has an advantage of enhanced noise reduction not only for thermal noise but also for 1/ f noise when a high-speed readout operation is required. The measurement of the noise performance of the 8K image sensor using the CMS with the interleaved pixel source follower method exhibits a low input-referred noise of 3.2 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> at 8K 120 frames per second, while 4.6 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> with the conventional single-source follower readout method. The measurement results match reasonably well with the analysis presented in this article, demonstrating the effectiveness of the interleaved pixel source follower method for high-resolution and high-framerate CISs.

Designing a Low-Power LNA and Filter for Portable EEG Acquisition Applications

A circuit with a low-power low-noise amplifier and a Gm-C ultra-low-power filter is proposed in this paper for portable electroencephalogram (EEG) acquisition applications. The proposed circuit contains a two-stage chopper-stabilized fully recycling folded cascode (TSRFC) amplifier and a second-order continuous-time Gm-C low pass filter (LPF) with ultra-low-power consumption. The noise and input offset are reduced using the chopper-stabilized technique. A two-stage amplifier that consists of composite transistors and a recycling structure is proposed for the amplifier. Compared to a typical folded cascode CMOS amplifier, the proposed design has higher DC gain and slew rate as well as lower input-referred noise. This circuit has an adjustable second-order Gm-C LPF with very low power consumption. The amplifier achieves a midband gain of 70 dB and a −3dB bandwidth in the range 0.1–212 Hz. Moreover, the amplifier is designed in 0.18- $\mu \text{m}$ CMOS process and the chip area of the proposed circuit with pads is $450\times 450\,\,\mu \text{m}^{2}$ . The adjustable LPF has a 100 Hz cut-off frequency. The proposed circuit has an input-referred noise of $0.7~\mu $ Vrms, (0.1 ~ 100Hz) and a power consumption of 380 nW at 1 V supply.

A novel programmable attenuator based low Gm-OTA for biomedical applications

In this paper, a novel programmable operational transconductance amplifier (POTA) using a pseudo resistor based programmable attenuator is proposed. A 4th order Butterworth programmable low pass filter (LPF) targeted for biomedical applications is designed using the proposed POTA. The proposed POTA and the LPF are designed and implemented in 0.18 ​μm CMOS technology with a supply voltage of 1 ​V and their performances are evaluated through post-layout simulations. The proposed POTA consumes a power of 27 ​nW, and its transconductance could be varied from 27 ​nA/V to 75 ​nA/V. It has higher linearity, dynamic range (DR) of 85.62 ​dB–79.46 ​dB and lower input-referred noise (IRN) of 33.15 μVrms to 58.65 μVrms than pre-input voltage attenuator based OTAs. The proposed LPF consumes a power of 208 ​nW. Its output dynamic range and IM3 lie in the range of (62.1 ​dB–49.26 ​dB) and (61.87 ​dB–53.14 ​dB) respectively. Its cutoff frequency can be varied from 100 ​Hz to 250 ​Hz.

A Generic Test Board for the Electrical Characterization of ULP and ULV Fully-Differential Integrated Analog Circuits

The characterization of ultra-low power (ULP) fully-differential/balanced amplifiers and active filters is challenging due to the incompatibility with the classical single-ended (SE) and 50 Ω impedance equipment. Interface circuits between the device under test (DUT) and the equipment are needed to perform the signal conversion and to work as voltage buffers. In this work, we propose a generic test circuits to be used in the characterization of ULP and ultra-low voltage (ULV) analog circuits. The test board includes balun transformers to the signal conversion, a high input impedance and low capacitance output driver and voltage regulators to provide the target DUT supply voltage. The characterization of the proposed PCB demonstrates a bandwidth of 30 MHz, output driver input impedance of 5 MΩ with 2.5 pF capacitance and low input-referred noise. The proposed circuit was applied to the electrical characterization of two fully-differential ULV and ULP analog integrated circuits.

High Input Impedance Low-Noise CMOS Analog Frontend IC for Wearable Electrocardiogram Monitoring

This brief presents a CMOS analog frontend (AFE) IC with high input impedance low input-referred noise, which for wearable electrocardiogram monitoring. The IC has three main parts, pseudo-differential chopper-stabilized instrumentation amplifier, switched capacitor filter, and low-power continuous–time <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${{\Sigma}} {{\Delta }}$ </tex-math></inline-formula> modulator. The pseudo-differential structure with chopper stabilization improves the input impedance, input–referred noise and chip area. Notably, we propose a new type of negative capacitor circuit to further boost the input impedance. Furthermore, the auto-zero technique is applied to the ripple reduction loop for suppressing the second harmonic ripple and maintain operation throughout the loop cycle. A dc servo loop suppresses the electrode dc offset. In <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process, the proposed AFE IC occupies an active area of 0.99 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , consumes 5.8/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$46.6~\mu \text{A}$ </tex-math></inline-formula> from a 1.8 V supply, and achieves an input impedance above 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}{{\Omega }}$ </tex-math></inline-formula> , a CMRR of 102 dB and a PSRR of 72 dB.

Noise Analysis and Design Considerations for Equalizer-Based Optical Receivers

Optical receiver front ends that are intentionally designed to have a bandwidth low enough that significant inter-symbol interference (ISI) is introduced are becoming commonplace. Although the resultant ISI must be removed using an equalizer, the lower bandwidth allows for higher gain in the front-end’s first stage, lower input-referred noise, and fewer gain stages. With fewer main-amplifier stages, power dissipation is reduced. The noise analysis of these front ends presents several challenges. This paper derives integrated input-referred noise for inverter-based shunt-feedback transimpedance amplifiers from first principles and highlights the importance of correctly estimating the gain and noise bandwidth of the receiver. The notion of the effective gain of the receiver is introduced, which is lower than the midband gain typically used in noise calculations. The analysis of the inverter-based TIA is used to discuss the important design tradeoffs depending on the type of equalizer used. Integrated input-referred noise is derived and compared for front ends using decision-feedback equalizers (DFEs), continuous-time linear equalizers, and feed-forward equalizers. The simulation results show that a DFE-based receiver achieves the lowest input-referred noise.