Low Device Stress Research Articles

Improved ultra voltage gain switched inductor based-Y-Source DC/DC converter with low device stress

ABSTRACT This article proposesanImproved ultra-high voltage gain Switched Inductor-Based Y-Source Converter (SI-YSC) forphotovoltaic (PV) and Fuel Cell (FC) applications. A single switch is employed to generate a high voltage boost at the load, and this topology provides a high voltage conversion ratio, minimal voltage stress on the switch, and continuous input current. The paper comprehensively examines passive components’ steady-state operation, design, and analysis. In addition, in order to comprehend the projected lifespan of the topology in different environments and operating conditions, the converter’s reliability is assessed to determine the mean time to failure of each component. To demonstrate the advantages of the proposed topology, an in-depth comparison is conducted between it and other Y source converters. The circuit design is verified using MATLAB/Simulink and a prototype model for an output power of 100 W. The results of this verification process are then analysed and discussed.

Q-EDR Hybrid Boost Converter Operation For High Gain With Low Device Stress

Abstract: The hybrid continuous-discontinuous mode (CCM-DCM) operation of non-isolated systems is proposed in this paper. boost converter with quadratic extended duty ratio (Q-EDR) for applications with high gain and low power. The inductors at the input while the EDR was in continuous conduction mode (CCM) The mode of operation of stage inductors is discontinuous conduction. (DCM) in order to reap the advantages of CCM and DCM operation. Interleaving's ripple in the low input current and low voltage The EDR stage switches' stress remains. With what is being half and half method of activity, the inductance worth of EDR stage significant decrease in the inductor. an additional decrease in switch voltage is accomplished during turn-on progress in the proposed activity, prompting huge decrease thus on exchanging losses. This lets the converter run at higher switching speeds. frequency, thereby reducing EDR inductors' size by 45 percent in this instance an experiment confirms the proposed idea. Simulink prototype for a two-phase Q-EDR operating at 30 V-40 V to 400 V output, a gain of more than 12 at duty close to 0.54. The converter has a peak efficiency of 95.5 percent. at a switching frequency of 135 kHz and 300 W for all silicon switches.

High gain interleaved DC-DC converter with ripple-free input current and low device stress

ABSTRACT A non-isolated DC-DC converter which yields high voltage gain and suitable for photovoltaic (PV) applications is described in this research article. The high gain converter proposed in this paper is synthesised by combining several voltage gain extension techniques viz. coupled inductors, voltage-lift capacitor, and diode-capacitor multiplier (DCM) cells. Since the input stage is interleaved, and the switches are operated complimentarily, the source current ripple is nullified and switch current rating is minimised. Due to the hybrid voltage gain extension techniques adopted while synthesising the converter, the voltage stress on the switches is only 10.5% of the output voltage. To validate the proposed concept, experimental results are obtained from 18 V-380 V, 150W prototype converter which is operated at 50 kHz. The proposed converter yields a voltage gain of 21.11 at 92.83% efficiency under full-load condition. During closed-loop operation, the proposed converter quickly settles down to its nominal output voltage of 380 V when the input voltage and load current values are subjected to step variations. The superior features of the proposed converter are highlighted by comparing it with similar and recent state-of-the art high gain converters.

Hybrid passivity‐based control of a three single‐phase star‐connected unidirectional five‐level rectifier with a space vector pulse‐width modulation algorithm for voltage balance

SummaryThe unidirectional multilevel rectifier has been used in numerous industrial applications due to its reduced active power switches, higher power density, and lower cost compared to conventional bidirectional converters. Recently, the unidirectional five‐level rectifier has been proposed for its lower device stress and the potential for extension to higher levels. However, it adopts a conventional linear proportional integral (PI) control strategy and sinusoidal pulse‐width modulation (SPWM) method, resulting in a complex control structure, particularly for the balance control of the midpoint voltage, and suboptimal dynamic performance. To address this issue and enhance system's large‐scale stability, a hybrid passivity‐based control (PBC) strategy, along with a simplified mathematical model, has been proposed. The hybrid PBC control strategy includes an outer loop active disturbance rejection (ADR)‐PI controller and inner loop PBC controller, providing a simple overall control structure and strong anti‐interference ability. Additionally, a space vector pulse‐width modulation (SVPWM) algorithm has been briefly introduced and applied to further improve the recovery and balance speed of the DC‐side capacitor voltages. Simulation and experiment results have validated the feasibility and effectiveness of the proposed hybrid PBC strategy and the SVPWM algorithm.

A Fractional Order Fast Repetitive Control Paradigm of Vienna Rectifier for Power Quality Improvement

Due to attractive features, including high efficiency, low device stress, and ability to boost voltage, a Vienna rectifier is commonly employed as a battery charger in an electric vehicle (EV). However, the 6k ± 1 harmonics in the acside current of the Vienna rectifier deteriorate the THD of the ac current, thus lowering the power factor. Therefore, the current closed-loop for suppressing 6k ± 1 harmonics is essential to meet the desired total harmonic distortion (THD). Fast repetitive control (FRC) is generally adopted; however, the deviation of power grid frequency causes delay link in the six frequency fast repetitive control to become non-integer and the tracking performance to deteriorate. This paper presents the detailed parameter design and calculation of fractional order fast repetitive controller (FOFRC) for the non-integer delay link. The finite polynomial approximates the non-integer delay link through the Lagrange interpolation method. By comparing the frequency characteristics of traditional repetitive control, the effectiveness of the FOFRC strategy is verified. Finally, simulation and experiment validate the steadystate performance and harmonics suppression ability of FOFRC.

Quadratic-Extended-Duty-Ratio Boost Converters for Ultra High Gain Application With Low Input Current Ripple and Low Device Stress

A new quadratic extended-duty-ratio (EDR) non-isolated boost converter is introduced here for ultra-high gain applications. The proposed converter is a combination of EDR boost converter and conventional quadratic boost converter. Quadratic boost converters can achieve high gain with lower component count while the EDR boost converter has low device stress while achieving high gain. A novel Quadratic EDR (Q-EDR) boost converter is proposed which is capable of attaining ultra high gain at moderate levels of duty with low voltage and current stress across different devices. Two different configurations of the proposed topology are presented with the interleaved version being able to reduce the current ripple further and the converter can be extended to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$M$</tex-math></inline-formula> -phases in both the configurations. Detailed analysis of a 4-phase converter is presented along with converter design considerations. The performance of the proposed topology is validated through a 1 kW, 4-phase hardware prototype operating at 20 V-36 V input to 600 V output at 60 kHz. Experimental results corresponding to both interleaved and non-interleaved converter configurations are presented. Experimental results show that the converter can attain a conversion ratio of 30 at an operational duty close to 0.64 in the interleaved configuration. The switch voltage stress is limited to 150 V and quadratic stage diode voltage stress is limited to be less than 100 V for 600 V output condition enabling the use of low voltage devices. The converter is able to achieve a peak efficiency of 95.82% for 36 V to 600 V operation at 660 W.

Power factor Enhancement in EV Charger fed by a New Modified BL Converter

Existing EV chargers use a strong non - linear diode bridge rectifier to deliver Direct Current voltage at the DC-DC converter's input, which degrades input AC current power factor. Due to these issues, typical battery chargers must eliminate the input bridge to improve power factor. This research paper main aim to improve the front end power factor by using bridge less landsman converter. It is combination of PFC converter and isolated fly back converter to operate between constant current and constant voltage modes. The modified PFC should achieve the constant DC-link voltage and improve the power factor up to unity. It also provide the improve in power quality, low device stress, low input and output ripples, and low input current harmonics when compared with bridge converter.

Research on Current Distribution Strategy Based on Interleaved Double Boost Converter

In the new energy DC microgrid system, most of the new energy outputs DC power with a low voltage level and a large fluctuation range, which cannot be directly connected to the network. It needs to be boosted by a DC–DC converter, then connected to the power grid or supplied with a DC load. On the premise that the traditional DC–DC converter cannot meet the requirements of high-power applications, the interleaved dual boost converter (IDBC) has been widely used because of its low input current ripple, low device stress and high-power density. It is necessary to maintain the current balance of each phase of the converter during a heavy load and to improve the efficiency during a light load. This paper analyzes the working principle of the six-phase IDBC and reduces the high order model to the low order model according to the symmetry. Due to the current imbalance caused by the mismatch of the parasitic parameters of each phase, two current distribution strategies are designed for different operating. To balance the current of each phase when the converter is overloaded, the relationship between the phase current, parasitic parameters and duty cycle is analyzed based on the state space average method. The estimated parasitic parameters are used to obtain the duty cycle compensation of each phase to eliminate the current imbalance. In addition, to improve the overall efficiency of the converter when the converter connects with a light load, the optimal power distribution coefficient is obtained according to the parasitic parameters to achieve the optimization of the input power, so as to improve the efficiency of the converter. Finally, the simulation results verify the feasibility and effectiveness of the proposed control strategy.

Discrete Time Adaptive Observer for Capacitor Voltage Estimation of MMC

Modular multilevel converters (MMC) are increasingly gaining its importance in HVDC, drive applications due to several attributes such as modularity, scalability, low device stress, excellent output voltage waveform. For MMC operations, it is important to accurately measure the voltages across the individual capacitors of submodules (SMs). These voltage sensors, while upgrading for high voltage applications, may cause a few concerns in terms of cost, complexity, and data acquisition system. To avoid all these, a discrete time adaptive observer (DTAO) is proposed in this article to observe the voltages across the capacitors of the SMs and use the observed values for closed-loop operation of the MMC. The proposed observer is designed by considering the parametric uncertainty in the MMC and its convergence is proved mathematically. Moreover, the DTAO is compared with existing observation techniques for MMC SM capacitor voltages. The efficacy of the proposed observer is shown through simulation and validated using an experimental setup.

Motor Stator Insulation Stress Due to Multilevel Inverter Voltage Output Levels and Power Quality

Multilevel Inverters (MLIs) are widely sought after in medium-voltage applications like electric ships, electric aircraft, and renewable energy integration due to excellent advantages like lower device stress, better power quality, and modularity. However, non-sinusoidal excitations from MLIs pose a serious problem to motor-insulation and lead to their premature breakdown. This paper investigates stress in medium-voltage motor insulation when the stator winding is excited by 3-, 5-, and 7-level multilevel inverter output waveforms. The effect of firing angle on insulation stress is also studied for each of the multilevel inverters. Results show that in addition to the number of output voltage levels, PWM wave shape is a critical factor which affects the insulation stress. Both these factors work together to impact the insulation health. A strong correlation is shown between the increase in the voltage root mean square (RMS) value and increase in dielectric stress when ignoring the dv/dt impact for a fixed DC input voltage and operating frequency of the inverter. Similarly, the dielectric stress in the stator insulation increased with an increase in firing angle for each of the MLIs. This paper shows a potential that both the RMSs can be optimized to reduce the insulation stress and improve the power quality of MLIs in medium voltage drives.

A Novel Robust Smooth Control of Input Parallel Output Series Quasi-Z-Source DC–DC Converter for Fuel Cell Electrical Vehicle Applications

Input parallel output series Quasi-Z-source dc-dc converter is a promising option for fuel cell electrical vehicle applications for its features of low device stress and high voltage ratio. Besides, the interleaved structure can reduce the input current ripple which can extend the lifespan of fuel cell system. In order to achieve better dynamic and steady-state performance for the converter, a novel smooth super-twisting sliding mode control (STSMC) method is designed in this article. The proposed control strategy is realized by constructing a novel smooth switch function in the zero domain of STSMC which comprises the advantages of both smooth feedback control and nonsmooth feedback control. Compared with the conventional STSMC, it guarantees strong robustness while possesses better smoothness namely excellent steady-state performance. Finally, a 200-W prototype has been created and described in detail. Simulation and experimental results validate the effectiveness of the proposed control algorithm.

Multicell Reconfigurable Multi-Input Multi-Output Energy Router Architecture

This article presents a multicell reconfigurable multi-input multi-output (MR-MIMO) power conversion architecture for multiport applications such as multisource energy router, battery balancer, and photovoltaic optimizer. The MR-MIMO architecture couples a large number of modular dc–ac cells with a single magnetic core which processes multiway bidirectional power flow. The system voltage and current ratings can be linearly extended and reconfigured by connecting the dc–ac cells in series or parallel. The MR-MIMO architecture decouples the voltage rating and current rating of the basic cells, and offers much lower device stress than traditional wide-operation range multiport dc–dc converters. The key contributions of this article include: 1) a multicell reconfigurable 12-winding MIMO converter with high performance across a wide range; 2) a hybrid time-sharing and phase-shift control strategy; and 3) a systematic method of designing multiwinding PCB transformers. The MR-MIMO architecture allows one power converter being used for multiple purposes through software reconfiguration. The work presented in this article proved that it is possible to gain significantly design flexibility in a multicell reconfigurable architecture without sacrificing the efficiency or power density. A 500-W 4-port energy router with 12 modular cells and a 12-winding transformer has been built and tested to verify the effectiveness of the proposed MR-MIMO architecture. The energy router maintains over 95% efficiency across a wide range of input and output voltage options.

Mitigation of Harmonics from Output of Cascaded H Bridge Multilevel Inverter Using SHE PWM and AI Technique: A Review

An extensive use of fossil fuel has led to an extreme increment of carbon footprint in the world globally. Glaciers are melting on the earth’s poles due to the greenhouse effect. Many such natural indications urge us to adopt renewable energy sources. In most cases, renewable power is generated in electrical form, which does not suit the existing grid requirements. Cascaded H bridge with multilevel inverter topology is promising in this context. The output of the multilevel inverter is near to sinusoidal. It has added advantages of low device stress, no need for step-up transformers, low common-mode voltage, near sinusoidal input current, low switching frequency, and reduced harmonics. The direct output of Cascaded H bridge multilevel inverters may not be suitable for many applications like integrating solar panel output with an existing grid where harmonic reduction is necessary. Various modulation techniques are available like sinusoidal pulse width modulation, space vector modulation, and selective harmonic elimination. Among the listed modulation techniques, selective harmonic elimination can be implemented with the low switching frequency, and it is suitable where low electromagnetic interference, low switching loss, and good power quality are required. To reduce the harmonics, one must solve the non-linear transcendental output equations of the cascaded H-bridge Multilevel inverter (CHB-MLI). Various Artificial Intelligent (AI) algorithms are introduced, and researchers have worked on eliminating harmonics or minimizing Total Harmonics Distortion (THD) from the output of CHB-MLI. This paper gives a review of the harmonic reduction using some of the well-known explored AI algorithms. It also provides insight into some of the unexplored algorithms in this area.

Power Factor Improvement in Modified Bridgeless Landsman Converter Fed EV Battery Charger

This work deals with the design and implementation of a new charger for a battery-operated electric vehicle (EV) with power factor improvement at the front end. In the proposed configuration, the conventional diode converter at the source end of existing EV battery charger is eliminated with the modified Landsman power factor correction (PFC) converter. The PFC converter is cascaded to a flyback isolated converter, which yields the EV battery control to charge it, first in constant current mode then switching to constant voltage mode. The proposed PFC converter is controlled using single sensed entity to achieve the robust regulation of dc-link voltage as well as to ensure the unity power factor operation. The proposed topology offers improved power quality, low device stress, and low input and output current ripple with low input current harmonics when compared to the conventional one. Moreover, to demonstrate the conformity of the proposed charger to an IEC 61000-3-2 standard, a prototype is built and tested to charge a 48 V EV battery of 100 Ah capacity, under transients in input voltage. The performance of the charger is found satisfactory for all the cases.

Efficiency‐optimised modulation technique of three‐level NPC inverter

The three-level NPC inverter has many advantages, such as the characteristics of high output power, low device stress, and low harmonic distortion of output waveform. It is widely used in the fields of high-voltage conversion and reactive power compensation. As the most commonly used multi-level inverter, three-level NPC inverter has its own disadvantage which is the NP potential fluctuations. It may lead to poor output performance even damage to the devices. Therefore, the problem of NP potential fluctuation of three-level NPC inverter has been the hotspot of its research. This paper presents an efficiency-optimised dual modulation wave carrier-based PWM (DMWPWM) strategy of three-level NPC inverter. First, the basic principle of traditional DMWPWM is analysed, and the deficiency of traditional DMWPWM modulation technique is described. Then, the efficiency-optimised DMWPWM strategy is deduced. Compared with traditional DMWPWM strategy, the new strategy inherits the advantage of traditional DMWPWM that the NP voltage balance can be maintained in any modulation index and power factor. Moreover, it can reduce the system switching loss which leads to efficiency improvement, and it is simple and easy to implement. Finally, the proposed modulation technique is verified by simulation.

Design and Analysis of the Low Device Stress Active Power Decoupling for Single-Phase Grid Connection for a Wide Range of Power Factor

Single-phase power converters suffer from the double frequency power pulsation. In voltage source inverters, the dc bus capacitor is designed to supply this double frequency current. The stringent dc bus voltage ripple specifications call for larger capacitance. This implies larger electrolytic capacitors. However, the electrolytic capacitor suffers from short-term life span, which consequently brings down the lifetime of the converter. As an alternative, active power decoupling (APD) ensures significant reduction in dc buffering requirement, thereby reducing the bus capacitance. This can make use of the film capacitors with better lifespan. In this paper, an APD scheme is designed and developed for the grid-connected system. Another important feature of the proposed scheme is that, it reduces the stress on the switches significantly while compared with existing APD solutions for all load power factors. The system is analyzed further to arrive at APD control conditions including the effect of grid filter inductance. The simulation and experimentation have been done to validate the proposed method. Additionally, the stress on the switches as a function of grid filter inductance is predicted theoretically and verified practically. The average stress on the switches is shown to be lesser than the existing solutions.

Non‐isolated high gain DC–DC converter with low device stress and input current ripple

In this article, a novel DC–DC converter with high voltage gain capability is presented. The proposed converter is synthesised from (i) a basic two-phase interleaved boost converter (IBC) which uses coupled inductors (CIs) instead of discrete inductors and (ii) diode-capacitor multiplier (DCM) cells to achieve higher voltage conversion ratio. The outputs obtained from the interleaved and the DCM stages are judiciously cascaded with the outputs obtained from the secondary winding of the CIs to enhance the voltage gain. The input current is almost ripple free due to the adopted interleaving mechanism. As voltage gain is extended using CIs and DCMs, the voltage stress on the semiconductor devices is minimal and only a fraction (10.5%) of the output voltage. Experimental results obtained from the 18 V/380 V, 150 W prototype converter, operating at a maximum efficiency of 94% under full-load condition, validate the proposed concept. Further, practical results obtained under closed-loop condition confirm that the converter yields a constant output of 380 V DC which is suitable for microgrid application.

Low conduction loss and low device stress three‐level power factor correction rectifier

A low conduction loss and low device stress three-level rectifier is proposed and the corresponding neutral-point voltage balance control scheme is presented in this study. Compared with the conventional rectifier, the MOSFET voltage rating can be reduced by half. The inductance and the volume of input inductor are reduced. The conduction losses can also be lowered because of the elimination of the front–end bridge rectifier and the adoption of synchronous rectification. The neutral-point voltage balance algorithm based on the average current-mode modulation is illustrated with constant frequency operation. To verify the theoretical analysis, a universal line input 100 kHz, 900 W prototype is built. The experimental results show that the input inductor volume is greatly reduced and the neutral-point voltage balance of the prototype is fulfilled considering various load conditions and dynamic processes. The proposed rectifier improves the efficiency by 2% under 90 V line input voltage compared with the conventional one.

High Power Current Sensorless Bidirectional 16-Phase Interleaved DC-DC Converter for Hybrid Vehicle Application

A new 16-phase interleaved bidirectional dc/dc converter is developed featuring smaller input/output filters, faster dynamic response and lower device stress than conventional designs, for hybrid vehicle applications. The converter is connected between the ultracapacitor (UC) pack and the battery pack in a multisource energy storage system of a hybrid vehicle. Typically, multiphase interleaved converters require a current control loop in each phase to avoid imbalanced current between phases. This increases system cost and control complexity. In this paper, in order to minimize imbalance currents and remove the current control loop in each phase, the converter is designed to operate in discontinuous conduction mode (DCM). The high current ripple associated with DCM operation is then alleviated by interleaving. The design, construction, and testing of an experimental hardware prototype is presented, with the test results included. Finally, a novel soft switch topology for DCM operation is proposed for future research, to achieve zero-voltage switching (ZVS), or zero-current switching (ZCS) in all transitions.

Design considerations of an SEPIC PFC converter for driving multiple lighting LED lamps

AbstractThis paper presents a single‐ended primary inductance power‐factor‐correction converter (SEPIC PFC) for driving multiple lighting LED lamps. With the aid of this converter, high power factor and high efficiency can be achieved by a simple single‐stage circuit with low device stress features. A burst‐mode dimming method is used to regulate the current and brightness of multiple LED lamps. A laboratory prototype is also built and tested. With the prototype, high power factor can remain under universal input voltage operation and individual lamp brightness control. Copyright © 2008 John Wiley &amp; Sons, Ltd.