Low Circuit Complexity Research Articles

Design of novel QCA-based half/full subtractors

Quantum-dot cellular automata (QCA) is an emerging nanotechnology and a possible alternative to the related issues of traditional complementary metal oxide semiconductors. It offers advantages such as high device density, high operating speed and ultra-low power consumption compared with semiconductor transistor-based technologies. Adder and subtractor circuits are the fundamental arithmetic logic circuits used in digital systems. The performance of digital systems can directly affect the operation of adder and subtractor circuits. In this direction, several QCA digital approaches have been devised to increase the performance of adder and subtractor circuits. In this paper, novel half/full subtractors using a single-layer scheme of QCA cells are proposed. The proposed structures have the most beneficial features of low power consumption, reduced area, less latency (clock delays) and circuit complexity (number of cells) compared to conventional designs. In addition, a novel controlled half adder/subtractor is presented. The modular layouts are verified with the freely available QCADesigner tool version 2.0.3. The results of computer simulations carried out on the proposed designs have confirmed the suitability of the proposed techniques.

Reliability, Dead-Time, and Feasibility Analysis of a Novel Modular Tankless ZCS Inverter for More Electric Aircraft

An increase in the demand of the electrical power in the more electric aircraft (MEA) with electrical equipment replacing the pneumatic and hydraulic equipment; the modular power converter (MPC) is needed for power conversion and power distribution in the MEA. The MPC is a promising technological solution for high voltage and high power conversion. The scalable configuration of MPC’s improves reliability and availability of the converter. This paper presents a novel modular zero current switching (ZCS) inverter for applications in the MEA. The proposed inverter achieves ZCS through a modular circuital configuration and eliminates the utilization of dead time. Elimination of dead time in the proposed topology will be helpful in proposing a low-complex control circuit for its integration with the 270-V dc power distribution architecture of the MEA. Moreover, with respect to MEA, the reliability and economic feasibility of the converter is also important, as reliability is a fundamental requirement in aircraft safety-critical equipment. A comparative analysis in terms of reliability, economic feasibility, and the effect of dead time on inverter output for the proposed inverter with respect to the conventional pulsewidth modulated inverter is presented in this paper. The operational and low loss features of the proposed converter are highlighted.

New Protection Technique Against Unidirectional MEUs for FIR Filters

As technology shrinks, multiple bits upsets (MBUs) are becoming an important problem in the reliability of digital designs exposed to radiation effects. In this paper, a new technique for the implementation of finite impulse response (FIR) filters is presented that provides protection against single and multi-unidirectional bit upsets (SEUs and MBUs), which have a lower circuit complexity and cost than traditional techniques like N-modular redundancy. Most of previous works has focused on single event upset (SEU), however, in this paper, a coding method based on Berger codes are presented and implemented on FPGA-based FIR filter. As the Berger coding covers all unidirectional faults, the MBUs are also handled in the proposed schemes. The effectiveness of the proposed technique has been evaluated using a dynamic partial reconfiguration-based fault injection platform. The implementation results of the proposed mitigation technique in comparison with traditional TMR method and previous mitigation techniques in the literature represent the effectiveness in terms of protection and implementation cost.

Ultra-Low-Energy Mixed-Signal IC Implementing Encoded Neural Networks

Encoded Neural Networks (ENNs) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks (HNNs) for the same number of nodes. Moreover, they have a lower density than HNNs in terms of connections, allowing a low-complexity circuit integration. The implementation of such a network requires low-complexity elements to take complete advantage of the assets of the model. This paper proposes an analog implementation of the ENNs. It is shown that this type of implementation is suitable for building network of thousands of nodes. To validate the proposed implementation, a prototype ENN of 30 computation nodes is designed, fabricated and tested on-chip for the ST 65-nm 1-V supply complementary metal-oxide silicon (CMOS) process. The circuit shows decoding performance similar to that of the theoretical model, and decodes a message in 58 ns. Moreover, the entire network occupies a silicon area of 16470 $\mu\text{m}^{2}$ and consumes 145 $\mu\text{W}$ , yielding a measured energy consumption per synaptic event per computation node of 68 fJ.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

Configurable network-on-chip router macrocells

This paper presents a configurable architecture for Network-on-Chip (NoC) router macrocells, and a methodology to streamline their design and configuration. The methodology addresses the typical problems experienced by design and verification engineers when coding highly configurable intellectual property macrocells at Register Transfer Level (RTL) with hundreds of parameters and thousands of resulting configurations. A NoC infrastructure for a Multi Processor System-on-Chip (MPSoC) may require tens or hundreds of router macrocells. Therefore, managing the configuration design space is becoming a bottleneck for the design and verification of many-core processing systems. The proposed generation flow is illustrated on a real-world NoC router core. Its configurable architecture is compliant with several NoC topologies such as Ring, Octagon, Spidergon and 2D mesh typically used in many-core processing platforms. The generation flow allows for a reduction in the database code size, up to 70% in our experiments, and a contraction of three orders of magnitudes of the verification space vs. conventional design flows of RTL macrocells. The validity of the approach is also confirmed by synthesizing the generated router macrocells in nanoscale CMOS technology. The achieved performance compare well to the state-of-the-art in terms of low latency and low circuit complexity.

An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter

A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18[Formula: see text][Formula: see text]m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.

An experimental study of coarse-grained reconfigurable system-on-chip-based software-defined radio

Software-dened radio (SDR) research deals with a mixture of hardware and software technologies, where RF operating parameters and components are to be set or altered by modiable software orrmware. This paper describes the coarse-grained recongurable array (CGRA) implementations of SDR architecture. This architecture is an extension of traditional SDR in complex adaptation strategies, such as highly reliable communications and efficient utilization of the resources and spectrum upgrade, through its internal states (performance) and hardware architecture. The proposed CGRA-based SDR implementation is based on dynamic partial reconguration methodology, which has the capability of reusing the same hardware module to handle different algorithms. This CGRA-based SDR provides greater exibility and adds new abilities without additional cost. Initially, the SDR system was simulated in the Agilent SystemVue environment to analyze the error boundaries of the proposed SDR architecture. Then the SDR system was coded in the Verilog hardware description language and implemented on top of CGRAs such as the MOLEN, MORPHOSYS, and ADRES recongurable system-on-chip (SoC) architectures. These SoC architectures were installed within the Xilinx Virtex 5 �eld-programmabl gate array to analyze the performance of SDR architectures in terms of area utilization, operational speed, power optimization, reconguration time, coprocessor execution time, preemption support, and relocation support of the system. The performance analysis indicates that the ADRES SoC architecture is suitable for dynamic partial reconguration and the MOLEN SoC architecture is more suitable for power, area, and speed requirements and low circuit complexity compared to other architectures.

VLSI Design of a Depth Map Estimation Circuit Based on Structured Light Algorithm

In this paper, depth map estimation circuit design based on structured light is proposed, wherein a projection light source and an image sensor are utilized in combination to achieve a depth map estimation chip, an accurate, low complex circuit is presented to measure the depth value of an object, and it is applied to 3-D television through depth image-based rendering technology to implement a multiview image display system. The chip that integrates image preprocessing, object segmentation, edge detection, and depth map quantization algorithms performs depth map estimation of objects accurately and quickly. Besides, the effect of human visual sensing effect is taken into consideration and the presented chip achieves a depth map quantified according to the nonlinear depth value in compliance with human visual system. Measurement results show that the chip that is verified using a Taiwan Semiconductor Manufacturing Company 0.18- $\mu $ m 1P6M CMOS process operates at 83.3 MHz with 19 845 gate counts and performs real time depth map estimation.

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

This paper investigates a novel cyclic time-to- digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digi- tizing the time interval between the rising edges of two input signals (Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitiv- ity to temperature, power supply and process (PVT) varia- tions. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. This converter also improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC re- duces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM). In this converter, the inte- gral nonlinearity (INL) and differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the pro- posed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theo- retical and simulation results confirms the benefits of the proposed TDC.

A digitally programmable gain amplifier for ultra-low-power applications

This paper presents a subthreshold CMOS digitally programmable gain amplifier for ultra-low-power signal processing applications. The subthreshold MOS transistor technique is used to achieve low-power consumption of the proposed circuit. The structure is constituted by a class-AB current amplifier which can handle a wide input signal. The gain of the digitally programmable gain amplifier is regulated by using current digital signal level without switch requirements; hence low circuit complexity, low power consumption and low number of devices can be obtained. Also both non-inverting and inverting amplifiers can be easily obtained into one single topology. Using additional resistors to convert the current to the voltage, single-input and differential-input digitally programmable voltage gain amplifiers can be obtained. The proposed circuit is simulated using 0.5 μm CMOS technology. The simulation results show that the proposed circuit consumes very low power from ±1.2 V power supply.

A New Triple-Slope Pipelined Time to Digital Converter by Stretching of Time

This study investigates a novel approach for pipeline time-to-digital converters (TDCs) which employs analog interpolation and time stretching techniques for digitizing the time interval between two input signals as well as increasing resolution. In the proposed converter, analog interpolation is performed based on a triple-slope conversion. This converter will be a 9-bit pipeline TDC which contains three time stretching amplifiers (TSAs) and four 2.5-b/stage TDCs. This converter does not use delay lines in its structure. It features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variations and high accuracy compared with the TDCs which have previously been proposed. Also, the time resolution, the dynamic range and the linear range of the TDC are improved. The proposed structure reduces the active chip area, the power consumption and the figure of merit (FoM). In addition, the integral nonlinearity (INL) and the differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the TDC is designed in TSMC 45-nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

A cascode-circuit configuration for grid-tied solar micro-inverters

This study proposes a solar micro-inverter that is connected to the AC grid through a cascode circuit configuration. Low system complexity and high circuit efficiency can be achieved through the concept of single-stage power conversion. A laboratory prototype is designed and implemented with DSP control to realize the maximum power point tracking function. The operating principles and design-related considerations of the proposed cascode micro-inverter are discussed in detail. The simulation and experimental results for the prototype circuit are shown to verify the feasibility of the proposed configuration.

A Piezoelectric Energy Harvester with High Efficiency and Low Circuit Complexity

This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in 0.18 μm CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.

Design of a Novel Pipeline Time-to-Digital Converter Based on Dual-Slope Interpolation and Time Amplification

ABSTRACTIn this paper, a novel pipeline time-to-digital converter (TDC) is presented which employs dual-slope analog interpolation and time amplification techniques for digitizing the time interval between two input signals. The proposed converter will be a 9-bit pipeline TDC which contains three 2.5 b/stage TDCs based on analog interpolation and a delay line TDC stage. The proposed converter features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variations, and high accuracy compared with the TDCs that have previously been proposed. This converter improves the resolution and the dynamic range. Also, the converter reduces the active chip area, the power consumption, and the figure of merit. In addition, the integral nonlinearity and differential nonlinearity errors are improved. In order to evaluate the idea, the proposed TDC is designed in TSMC 0.18μm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

A CMOS CURRENT-MODE LOW POWER RMS-TO-DC CONVERTER

In this paper a low-power current-mode RMS-to-DC converter is proposed. The converter includes two-quadrant squarer/divider and the first-order low-pass filter cell, both of them use MOS translinear loops. The RMS-to-DC converter has low power consumption (< 0.75μW), low supply voltage (0.8 V), wide input range (from 40 nA to 500 nA), low relative error (< 3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

A CURRENT-MODE RMS-TO-DC CONVERTER BASED ON TRANSLINEAR PRINCIPLE

In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (<1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative error (<3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

A CMOS fifth-derivative Gaussian pulse generator for UWB applications

A CMOS fifth-derivative Gaussian pulse generator is presented for ultra-wideband (UWB) applications. The design exhibits low power consumption, low circuit complexity, and a precise pulse shape to inherently comply with the FCC spectrum mask for indoor UWB applications without the need for a filter. The pulse generator is implemented with a 1.8-V, 0.18-μm CMOS process. The small core chip size of the pulse generator is only 217 × 121 μm2 because of its all digital circuit design. The measured fifth-derivative Gaussian pulse has a peak-to-peak amplitude of 158 mV and a pulse width of 800 ps. The average power dissipation is 0.6 mW with a pulse repetition frequency of 50 MHz.

Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT transforms have been proposed that offer superior compression performance at very low circuit complexity. Such approximations can be realized in digital VLSI hardware using additions and subtractions only, leading to significant reductions in chip area and power consumption compared to conventional DCTs and integer transforms. In this paper, we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio. The proposed DCT approximation is a candidate for reconfigurable video standards such as HEVC. The proposed transform and several other DCT approximations are mapped to systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology.

Low-voltage FGMOS squarer/divider-based analog building blocks

This paper presents a new low-voltage floating gate MOS (FGMOS)-based current-mode squarer/divider circuit. The low-voltage operation is obtained by replacing the PMOS transistor used to bias the conventional circuit with two-input FGMOS. The proposed circuit offers advantage of two-quadrant operation, low supply voltage (0.85 V) requirement, low circuit complexity and low noise as compared to the conventional one. The proposed circuit is then used as basic building block to develop full Gaussian function generator and RMS-to-DC converter. The simulations are performed in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Spectre simulator of Cadence.