Low Voltage Electrostatic Discharge Research Articles

Design of a LVTSCR triggered SCR device for low voltage ESD protection

In this paper, a novel silicon-controlled rectifier (SCR) electrostatic discharge (ESD) protection device, called low voltage triggered SCR (LVTSCR) triggered SCR (LVTSCRTSCR), is proposed for 3.3 V I/O protection applications in 0.18 μm CMOS technology. One side of the device is the traditional LVTSCR structure, and other side is the traditional SCR structure. The two structures are connected by a floating P+ diffusion layer. The working principle of LVTSCRTSCR was verified by the TCAD simulation results and TLP test results. The test results show that the triggering voltage of LVTSCRTSCR is determined by the traditional LVTSCR, with a value of 9.850 V. The holding voltage of the device can be effectively improved by increasing the size of the floating diffusion layer D4. When D4 = 6 μm, the holding voltage can be 4.491 V, suitable for 3.3 V I/O.

A novel low trigger voltage low leakage SCR for low-voltage ESD protection

Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 °C is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.

MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application

In this work, a new low voltage-triggered silicon-controlled rectifier named MTSCR is realized in a 65 nm CMOS process for low voltage-integrated circuits electrostatic discharge (ESD) protections. The MTSCR incorporates an external NMOSs-string, which drives the internal NMOS (INMOS) of MTSCR to turn on, and then the INMOS drive SCR structure to turn on. Compared with the existing low trigger voltage (Vt1) ESD component named diodes-string-triggered SCR (DTSCR), the MTSCR can realize the same low Vt1 characteristic but less area penalty of ~44.3% reduction. The results of the transmission line pulsing (TLP) measurement shows that the MTSCR possesses above 2.42 V holding voltage (Vh) and a low Vt1 of ~5.03 V, making it very suitable for the ESD protections for 1.8 V input/output (I/O) ports in CMOS technologies.

A Novel Voltage Divider Trigger SCR With Low Leakage Current for Low-Voltage ESD Application

In this article, a novel voltage divider trigger silicon-controlled rectifier (VDTSCR) with low trigger voltage and low leakage current for electrostatic discharge (ESD) protection applications has been proposed and verified in a 65-nm epitaxial CMOS process. The trigger structure formed by a voltage divider and an nMOS is introduced to the proposed structure. The voltage divider composed of two series capacitors can control the turn-on of the nMOS, and the nMOS current can trigger the silicon-controlled rectifier (SCR) device to reduce the trigger voltage of the proposed device. Such triggering structure is fully embedded in the proposed device for saving area. The measurement results show that the proposed device can achieve a low trigger voltage of 2.88 V, a low leakage current of 120 pA, and the second breakdown current of 4.35 A for a 1.2-V application. Furthermore, the VDTSCR device can be immune from the risk of latch-up and false triggering. Due to the low trigger voltage and low leakage current of the proposed device, it is suitable for low-voltage and low-power applications.

The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.

Compact and Low Leakage Devices for Bidirectional Low-Voltage ESD Protection Applications

In advanced charged device model (CDM) protection engineering, it is necessary to provide dedicated dual-directional electrostatic discharge (ESD) protection between input/output (I/O) and ground (GND) to discharge the large amount of charge stored in the silicon substrate efficiently. This letter presents two improved bidirectional and low-voltage silicon-controlled rectifiers (BLVSCR-type1 and BLVSCR-type2), which are composed of two diode-triggered SCRs of opposite polarity in parallel. By improving the device structure and metal connection, the BLVSCR-type1 and BLVSCR-type2 can offer robust ESD capabilities. Compared with the conventional bidirectional direct-connected SCR (BDCSCR), experimental results show that the proposed BLVSCR-type1 can render a three order of magnitude reduction in the leakage current at a 1.2V I/O port and more stable parasitic capacitance characteristic. Moreover, the BLVSCR-type2 can possess a compact layout area reduced by as much as 35% when comparing to BLVSCR-type1.

Design of a Dual-directional Diode-triggered SCR for Low Voltage ESD Protection

A novel dual-directional diode-triggered silicon controlled rectifier (DDTSCR) for low voltage electrostatic discharge (ESD) protection was designed and realized in a 0.18-µm CMOS process. Compared to the single-directional diode-triggered SCR (SDTSCR), the DDTSCR has dual-directional ESD protection performance due to the symmetric structure, and its ESD protection efficiency per unit area is about 2 times larger than that of SDTSCR under opposite ESD stresses, while remaining the similar trigger voltage of 1.68 V and the figure of merit. The human body model robustness of the DDTSCR measured by the transmission line pulse system is up to 8000 V with an area of 1400 µm2, suitable for low voltage ESD protection requirements.

Design and analysis of different trigger techniques for ESD clamp circuit in 0.5-µm 5 V/18 V CDMOS process

In this work, gate-driven, substrate-triggered and gate-substrate-triggered techniques for both 5V NMOS-based and 18V NLDMOS-based power clamps under electrostatic discharge (ESD) stress were investigated in details. Schematics of the three trigger designs were depicted and their physical mechanisms were studied at first. To verify and make comparisons of their performance, they were fabricated in a standard 0.5-μm 5V/18V CDMOS process and characterized by transmission line pulse (TLP) test system, respectively. Experimental results show that 5V NMOS-based power clamp with substrate-triggered technique has the lowest trigger voltage (∼8.37V) and the highest failure current (∼3.58A), and 18V gate-substrate-triggered design based on NLDMOS has low trigger voltage (∼34.02V) and greatest robustness (It2=3.32A). Therefore, as for low-voltage NMOS-based ESD power clamps, substrate-triggered design obtains the most superior ESD protection performance; but for high-voltage power clamps, gate-substrate-triggered technique can make NLDMOS actualize uniform current conduction and better ESD robustness.

Silicon-Controlled Rectifier for Electrostatic Discharge Protection Solutions With Minimal Snapback and Reduced Overshoot Voltage

An electrostatic discharge (ESD) protection structure constructed by the stacking of multiple anode gate–cathode gate directly connected silicon-controlled rectifiers (DCSCRs), fabricated in a 0.18- $\mu \text{m}$ CMOS technology is reported in this letter. Two embedded diodes in the DCSCR dictate the turn-ON mechanism and hence give rise to a trigger voltage equal to twice the diode’s turn-ON voltage. This approach enables the DCSCR to offer a diode-like transmission line pulsing IV characteristic with a minimal snapback and a SCR-like high-ESD robustness. At 25 °C, DCSCR has an acceptable nanoampere-level leakage current. Besides, it is verified that the DCSCR can significantly reduce overshoot voltage when stressed by very-fast-rising pulses. As such, an ESD clamp constructed by stacking a selected number of DCSCRs can offer a flexible trigger/holding voltage and is suitable for low and medium voltage ESD protection applications.

Optimized pMOS-Triggered Bidirectional SCR for Low-Voltage ESD Protection Applications

In this paper, an optimized pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) fabricated in a 0.18- \(\mu \) m CMOS technology is proposed as a viable electrostatic discharge (ESD) protection solution. Capable of working under both the power-ON and power-OFF conditions, this structure is verified to provide bidirectional ESD protection performance superior to those reported in the literatures. Critical ESD parameters, such as the trigger voltage, holding voltage, and leakage current, can be flexibly adjusted via layout changes. With a low trigger voltage, a small ESD design window, a high robustness, and a small silicon area consumption, the PTBSCR is very suitable for low-voltage and low-power ESD protection applications.

Minimizing Multiple Triggering Effect in Diode-Triggered Silicon-Controlled Rectifiers for ESD Protection Applications

The diode-triggered silicon-controlled rectifier (DTSCR) is frequently used for low-voltage electrostatic discharge (ESD) protection applications, but such a device can exhibit two snapbacks and consequently can possess an undesirable large trigger voltage. This letter investigates the mechanism underlying the DTSCR's multiple triggering. An improved DTSCR for reducing the second trigger voltage and increasing the ESD safe margin is proposed and verified in a 65-nm complementary metal-oxide-semiconductor process. The improved DTSCR's turn-on characteristic is also discussed.

Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS

This paper reports design, analysis and optimization of a new low-parasitic, very-low-triggering-voltage dual-directional silicon-controlled rectifier (VLTdSCR) type electrostatic discharge (ESD) protection structure and its cross-coupling ultra-low-triggering ESD protection circuitry (CULTdSCR) implemented in a commercial 0.18 μm CMOS. Mixed-mode ESD simulation-design technique is used to verify the new embedded punch-through and gate cross-coupling ESD trigger-assisting techniques devised to achieve ultra-low ESD triggering for SCR-type ESD protection in CMOS. Experiment shows a record low ESD triggering voltage (Vt1) of 3.83 V, noise figure (NF) of 0.2 dB, parasitic ESD capacitance (CESD) of 150 fF and prompt response to very fast ESD pulses with rising time (tr) down to 100 pS. The new ESD design achieves a very high dual-directional charged device model (CDM) ESD protection capability of ~7 V/μ m2.

Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

The physical mechanisms triggering electrostatic discharge (ESD) in high voltage LDMOS power transistors (> 160 V) under transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP) stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.