Low Voltage Differential Signaling Transmitter Research Articles

Development of a front-end electronics for thin-gap resistive plate chamber

To cope with the challenge of high hit rates in some applications, the new-generation large-area Resistive Plate Chamber (RPC) with 1 mm thin gap was proposed. Compared to the RPC generation presently, the signal of the thin-gap RPC is much weaker (of the order of hundreds of μV) and faster (pulse width of about 5 ns). Hence a new-generation Front-End (FE) electronics needs to be developed for the thin-gap RPC. The FE board contains 8 independent electronic channels, each with an amplifier, a discriminator, and a Low-Voltage Differential Signaling (LVDS) transmitter. The amplifier is made of discrete components, with particular emphasis on SiGe:C transistors. A simplified but stable power system is designed for the FE board, and its status can be monitored in real-time. The test results show that the overall charge gain of the FE amplifier reaches 0.4 mV/fC, with very low noise (lower than 700 μV RMS with up to 10 pF input detector capacitance), and good linearity when the amplitude of the input amplitude is lower than 3 mV. The -3-dB bandwidth of the amplifier reaches 154 MHz. The jitter caused by the electronics (including amplifier, discriminator and LVDS transmitter) is around 10 ps when the threshold voltage is higher than 20 mV. The maximum event rate per channel exceeds 20 MHz. The cosmic ray test was conducted with two FE boards mounted on a 1 mm thin-gap RPC of 1.4 × 0.4 m2 area. The efficiency of the detector system reaches 95% when the threshold voltage is 20 mV, with almost no accidental coincidence event. The overall time resolution of the detector system is 484 ps. The performance of our FE electronics satisfies the requirement of the thin-gap RPC.

A fully integrated and high precision 350 mV amplitude regulated LVDS transmitter compensating PVT variations

A low cost solution and high precision output amplitude regulation for Low-Voltage Differential Signaling (LVDS) driver targeted for TIA/EIA-644-A standard is reported. The proposed architecture has high tolerance towards internal resistors variations by adapting continuous calibration of output amplitude through a negative-feedback loop. It eliminates the requirements of high precision or expensive external resistor or post-fabrication calibration. Fabricated in 0.13-μm CMOS with a supply voltage of 3.3 V, the prototype exhibits regulated 700 mV output amplitude which is able to compensate for process, voltage and temperature (PVT) variations.

An Integrated LVDS Transmitter–Receiver System With Increased Self-Immunity to EMI in 0.18-um CMOS

This paper presents the design of an integrated low-voltage differential signaling (LVDS) transmitter–receiver system with a superior immunity to electromagnetic interference (EMI). The effects of injected RF interference on the differential communication bus between the proposed and typical LVDS transmitter and receiver front-ends are presented and explained mathematically. The design of a proposed wide input common-mode range LVDS receiver with an increased noise margin is discussed in detail. Transverse electromagnetic (TEM) cell measurements confirm that the proposed LVDS transmitter–receiver yields a worst-case bit error rate (BER) of 0.1 for an injected 30-dBm EMI signal at 840 MHz, while the typical transmitter–receiver pair fails with a BER of 0.5 for EMI levels as low as 23 dBm at frequencies ranging from 650 to 800 MHz, 820 to 860 MHz, and at 560 MHz. The discussed LVDS transmitter–receiver circuits were designed using the UMC 0.18- $\mu \text{}$ m CMOS process with a supply voltage of 1.8 V.

An Integrated LVDS Transmitter in 0.18-<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula>m CMOS Technology With High Immunity to EMI

This paper presents an on-chip design topology that compensates the effects of electromagnetic interference (EMI) in a low-voltage differential signaling (LVDS) transmitter. The proposed structure enables the transmitter to maintain a wide differential opening by achieving a superior common-mode level independent driving current and common-mode feedback closed-loop gain. Direct power injection measurements illustrate that the proposed LVDS transmitter structure demonstrates a superior EMI immunity as it maintains an eye opening of at least 100 mVp-p in presence of a conductive EMI injection ranging from 150 to 2 GHz with an amplitude of up to 9 Vp-p. Additionally, transverse electromagnetic cell measurements validate the radiated immunity of the proposed integrated LVDS transmitter in presence of an EMI injection of 30 dBm (150 kHz–2 GHz). This EMI robust LVDS transmitter was designed using the UMC 0.18- $\mu$ m CMOS process.

Design and realization of 1.3 Gb/s off-chip transmission circuitry using 0.35 μm CMOS technology

Low-voltage-differential-signaling (LVDS) is one of the very popular technologies which simultaneously addresses low dynamic power consumption and high data rate transmission in modern high speed circuit applications. In this paper, system level integration design approach is applied to design LVDS transmitter featuring high off-chip data rate. Full wave electromagnetic simulation technique was adopted to accurately characterize possible couplings and parasitic effects induced from the off-chip components which then acted as the termination of the output circuitry. Common mode feedback was included to perform fine tuning on the offset leading to much higher overall precision. Meanwhile, generation of the controlled current and voltage across termination was guaranteed through the introduction of a constant transconductance bias network. The design was implemented using TSMC 3.3 V 0.35 μm CMOS technology with overall chip size of 0.923 mm2. At a DC power consumption level of 29.4 mW, the LVDS transmitter exhibited an off-chip data rate of 1.3 Gb/s validated through measurements.

Design of high speed LVDS transceiver ICs

The design of low-power LVDS (low voltage differential signaling) transceiver ICs is presented. The LVDS transmitter integrates a common-mode feedback control on chip, while a specially designed pre-charge circuit is proposed to improve the speed of the circuit, making the highest data rate up to 622 Mb/s. For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers. In addition, the LVDS receiver also supports the failsafe function. The transceiver chips were verified with the CSMC 0.5-μm CMOS process. The measured results showed that, for the LVDS transmitter with the pre-charge technique proposed, the maximum data rate is higher than 622 Mb/s. The power consumption is 6 mA with a 5-V power supply. The LVDS receiver can work properly with a larger input common mode voltage (0.1–2.4 V) but a differential input voltage as low as 100 mV. The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/s. The chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.