Low-voltage Current Mirror Research Articles

Innovative feedback approach for high-performance low-voltage current mirror

The paper presents an approach to increase the performance in terms of input and output resistance of a low voltage flipped voltage follower (FVF) based current mirror. The proposed technique consists of substituting the main output transistor with a network of transistors in a feedback arrangement, designed to improve the output resistance. Furthermore, a low saturation onset transistor approach is used to improve the performance. Such an approach also helped in reducing the input resistance of the current mirror, which ranges in ohms. A wide current range of up to 1 mA is achieved at a minimal current transfer error of 0.38 %. This feedback mechanism-based current mirror exhibits an output resistance of 29.61 GΩ, an input resistance of 30.45 Ω, and a bandwidth of 1.464 GHz. The proposed current mirror runs on ±0.5 V supply voltage. The robustness of the proposed circuit is evaluated through process corner analysis, temperature mismatch assessment, and Monte-Carlo simulations. The performance characteristics of the proposed current mirror have been validated and simulated using Cadence Virtuoso and Spectre simulations on 0.18 μm UMC technology. The validation process included both pre-layout and post-layout simulation results.

Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower

The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

Low-voltage wide-range high-impedance flipped voltage follower current mirror

Low-voltage wide-range high-impedance flipped voltage follower current mirror

A Low-Voltage Current Mirror for Transconductance Amplifiers

In this study, a low-voltage current mirror to use in differential pair as an active load is introduced. The proposed current mirror which can operate at ±0.5 V has high output impedance and low input impedance. The proposed structure employs the principle of the voltage level-shifting for PMOS transistors. The voltage level-shifting operation has been achieved by using bulk voltage at this structure. Also, spice simulations justify the highly good performance of this current mirror with a bandwidth of 11 GHz by using external capacitor at input current of 200 μA.

A four quadrant high-speed CMOS analog multiplier based on the flipped voltage follower cell

In this work the design and implementation of a High-Speed Four-Quadrant CMOS Analog multiplier is presented. The proposed multiplier uses the Gilbert cell as the main core. However, instead of processing both input and output signals in voltage or current mode, the “x” input signal is applied in voltage mode while the “y” input signal and “o” output signal are processed in current-mode. This approach is achieved by means of using very-low-impedance nodes at the “y” and “o” ports which also helps to enhance the overall bandwidth of the proposed multiplier. Both very-low-impedance nodes are implemented using the Flipped Voltage Follower (FVF) as high-speed high-performance low-voltage current mirror. The implemented circuit shows a bandwidth of 260 MHz for a 50Ω‖30pF load, presents a 1.5% THD at 100 MHz, and consumes 7.5 mV using a ±1 V symmetric power supply. In order to validate theory and simulations, a prototype of the multiplier was fabricated and tested using a 0.5 μm CMOS standard fabrication process; a silicon area consumption of 520 μm × 70 μm was observed. Measurements shows that the proposed multiplier is suitable for its implementation in the low corner of the Very High Frequency (VHF) band.

A 16 ns, 28 fJ Wide-Range Subthreshold Level Converter Using Low-Voltage Current Mirror

This paper proposes a high-speed and energy-efficient low-voltage current mirror-based level converter (LCM LC) which can perform a wide-range conversion of a subthreshold input signal (180 mV) to an above-threshold output signal (1.2 V). The proposed level converter utilizes low-voltage current mirror (LCM) circuit with high-threshold-voltage (hvt) PMOS devices in the pull-up network, which drives a switching current from high supply rail to output node during the high-to-low transition of an input signal to ensure wide-range conversion. The driving capability of the pull-down network in LCM LC is increased by employing inverse-narrow-width-effect (INWE)-aware low-threshold-voltage (lvt) NMOS devices in order to perform a high-speed operation. This level converter employs multi-threshold CMOS devices and is implemented in 45 nm technology using Cadence Virtuoso. The LCM LC exhibits a delay of 16.4 ns, energy per transition of 28.1 fJ and static power of 412 pW which are observed using Spectre circuit simulator for the target conversion from 0.2 to 1.2 V at a signal frequency of 1 MHz.

Low-Voltage Flipped Voltage Follower Cell Based Current Mirrors for High Frequency Applications

The paper proposes low-voltage current mirrors namely low-voltage current mirror (LVCM) and flipped voltage follower based low-voltage current mirror (FVFLVCM) with high bandwidth. The stability of the proposed circuits has been performed by time-domain approach and frequency domain approach using Routh–Hurwitz stability criteria and phase margin calculations, respectively. The bandwidth of the proposed FVFLVCM has also been enhanced using resistive compensation technique. The proposed LVCM and FVFLVCM have wide input current range of 0–100 µA and 0–150 µA, low DC error of 5.9% and 4.9%, low DC power dissipation of 110.39 µW and 99 µW, high bandwidth of 367 MHz and 624 MHz, low input impedance of 16.3 KΩ and 12.3 KΩ, low THD of 0.26% and 1% and low output noise of 2.25 nA and 2.83 nA over 100 MHz, respectively. The results have been simulated using SPICE in the TSMC 0.18 µm CMOS technology and are presented to validate the effectiveness of the proposed current mirrors.

An ultra low-power current-mode clock and data recovery design with input bit-rate adaptability for biomedical applications in CMOS 90 nm

This paper presents a clock and data recovery (CDR) topology that can adjust the power consumption with its input bit-rate. Current-mode structures are utilized to control the power consumption. The system is comprised of a phase detector, a charge pump, a second-order filter, a voltage-to-current converter, a bias controller, and a current controlled oscillator. In order to attain an ultra-low power profile, subthreshold source-coupled logic (STSCL) is used to implement the system blocks. A modified version of low-voltage current-mirror is proposed and utilized to improve the thermal stability of the CDR structure. The proposed current mirror improves the oscillator frequency variation more than 20 times. The CDR is simulated in 90 nm standard CMOS process with VDD = 1 V. It can recover clock frequencies between 1 MHz and 25 MHz. The corresponding power consumption is between 195 nW and 450 nW, and the measured deterministic-jitter is less than 100 ns.

Optical interaction in active analog circuit elements

This publication introduces (spectral) photon emission (PEM) and electro-optical frequency mapping (EOFM/LVI) measurements to analog circuit elements (simple, cascode and low-voltage current mirrors). Different operating conditions of the devices are probed and the voltage dependence of the signals is analyzed. Results partly show close similarities to optical probing of digital IC's, but also differences in voltage dependence and signal levels due to more complicated voltage and signal distributions along the devices.

DESIGN LOW VOLTAGE CURRENT MIRROR AT 32NM REGIME

As the technology moving towards lower voltage for high stability and accurate performance. We design low voltage current mirror using IGFET, FDSOI, CNTFET.These transistor moving towards low-voltage high-speed performance. Here in this paper, we have design low voltage current mirror for Accurate duplication of current. To obtain accurate duplication of current we verify the performance of low voltage current mirror on FDSOI and CNTFET Transistor having 32nm technology.The circuit is simulated with 32nm technology for FDSOI and CNFET. They operate at lower power supply than IGFET. The simulation results show the improvement in knee voltage 1.7v and 1.3v for the current mirror.

A new low voltage level-shifted FVF current mirror with enhanced bandwidth and output resistance

ABSTRACTThis paper proposes a new high-performance level-shifted flipped voltage follower (LSFVF) based low-voltage current mirror (CM). The proposed CM utilises the low-supply voltage and low-input resistance characteristics of a flipped voltage follower (FVF) CM. In the proposed CM, level-shifting configuration is used to obtain a wide operating current range and resistive compensation technique is employed to increase the operating bandwidth. The peaking in frequency response is reduced by using an additional large MOSFET. Moreover, a very high output resistance (in GΩ range) along with low-current transfer error is achieved through super-cascode configuration for a wide current range (0–440 µA). Small signal analysis is carried out to show the improvements achieved at each step. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology. In the proposed CM, a bandwidth of 6.1799 GHz, 1% settling time of 0.719 ns, input and output resistances of 21.43 Ω and 1.14 GΩ, respectively, are obtained with a single supply voltage of 1 V. The layout of the proposed CM has been designed and post-layout simulation results have been shown. The post-layout simulation results for Monte Carlo and temperature analysis have also been included to show the reliability of the CM against the variations in process parameters and temperature changes.

ANALYSIS OF DIFFERENT TYPES OF CURRENT MIRROR IN 45NM TECHNOLOGY

Momentarily the analog electronics has made low vol tage, low power circuit designs extremely adorable . As power is the product of supplied voltage and flowing current through the circuit so power id directly varies with supplied voltage .That means reducing supply voltage is a direct way to achieve low power consumption. Low Voltage and low power current mir rors are essential blocks of analog IC design.

High frequency flipped voltage follower with improved performance and its application

In this paper a wideband flipped voltage follower (FVF) with low output impedance at high frequency has been proposed. Inductive-peaking-based bandwidth extension technique is employed in the FVF cell. The small signal high-frequency analysis of both conventional and proposed FVF has been done. It is shown in analytical derivation of the proposed FVF that by adding an inductive element in the feedback path, the bandwidth is enhanced. Simulation results show that bandwidth extension ratio (BWER) of proposed FVF is about 2.00, without extra dc power dissipation. A wideband low voltage current mirror has been developed by using proposed FVF in place of conventional FVF and by doing so, BWER of 2.98 has been achieved. The performances of circuits are verified in TSMC 0.18μm CMOS, BSIM3 and Level 49 technology with 1.5V power supply and by using Spectre simulator of Cadence.

Quasi-floating gate MOSFET based low voltage current mirror

This paper demonstrates the use of quasi-floating gate MOSFET (QFGMOS) in the design of a low voltage current mirror and highlights its advantages over the floating gate MOSFET (FGMOS). The use of resistive compensation has been shown to enhance the bandwidth of QFGMOS current mirror. The proposed current mirror based on QFGMOS has a current range up to 500μA with offset of 2.2nA, input resistance of 235Ω, output resistance of 117kΩ, current transfer ratio of 0.98, dissipates 0.83mW power and exhibits bandwidth of 656MHz which increases to 1.52GHz with resistive compensation. The theoretical and simulation results are in good agreement. The workability of the circuits has been verified using PSpice simulation for 0.13μm technology with a supply voltage of ±0.5V.

1.5-V Complex Filters Using Current Mirrors

The derivation of complex filter topologies according to leapfrog and topological emulation techniques is presented in this brief, where the employed active elements are low-voltage current mirrors. Thus, the offered benefits are the capability of operating in a modern low-voltage environment, the absence of resistors, and the electronic tuning of the frequency characteristics. A 12th-order complex filter function has been realized by employing the aforementioned techniques, and the performance of the corresponding topologies, fabricated in an Austria Mircro Systems 0.35-μm complementary Metal-Oxide-Semiconductor process, has been experimentally verified.

DC-gain enhancement technique for differential current-mode integrators

A DC-gain enhancement technique for Q-tuning is presented for low-voltage current-mirror based differential current-mode integrators. A tunable active resistor makes it theoretically possible to obtain infinite DC-gain without making any modification to the operating point of the integrator. Simulation results agree well with the technique.

Universal biquad filters using low-voltage current mirrors

Novel Single Input Multiple Output (SIMO) and Multiple Input Single Output (MISO) current-mode universal biquad topologies are introduced in this paper. The proposed topologies have been realized by employing low-voltage current mirrors as active elements. As a result, an absence of resistors is achieved in the derived filter topologies; also only grounded capacitors are required. The resonant frequency of the filters can be electronically controlled by an appropriate dc current. In addition, the derived filters offer the feature of orthogonal adjustment between the resonant frequency and Q factor. The behavior evaluation of the proposed filters has been performed through a test chip prototype fabricated in AMS 0.35 μm CMOS technology.

A very-high output impedance charge pump for low-voltage low-power PLLs

This article presents the design of a high output compliance, very-high output impedance single-ended charge pump implemented using a new low-voltage current mirror. The output current is sampled and a feedback loop forces it to be equal to the desired reference current. This results in a very-high output impedance over a very wide output voltage range, accurate Up/Down current matching, and low transient glitches. The proposed charge pump was implemented using STMicroelectronics 1-V 90-nm CMOS process. Simulations using Spectre show that the Up/Down output currents remain constant and matched within 1% over a charge pump output voltage ranging from 119 to 873mV. Monte Carlo process variations and mismatch simulations indicate that the 1-σ standard deviation between the Up and Down current components is 1.4μA, or 6.8% of the nominal 20μA charge pump current at either end of the output voltage range.

Low voltage current mirrors with enhanced bandwidth

This paper presents an improved low voltage cascode and flipped voltage follower (FVF) based current mirror with the enhancement of the bandwidth obtained by using a compensation resistor between the gates of the primary transistor pair. In this technique a carefully determined resistance is used in the diode connected MOS transistor of the current mirror for enhancing the bandwidth. Active realization of the compensation resistance using MOS operating in the triode region has also been applied to both the cascode and FVF based current mirror circuits. The proposed circuits have been simulated using PSpice for 0.25 μm CMOS technology and the obtained results are compared with their uncompensated topologies to show their effectiveness.

FGMOS Current Mirror: Behaviour and Bandwidth Enhancement

This paper presents a high performance, resistively compensated low voltage current mirror using floating gate MOSFETs (FGMOS). The compensation technique desensitizes the output current and input compliance voltage with respect to the process generated variations in the threshold voltages of the mirroring transistors. Theoretical and simulation results exhibit an appreciable increase in bandwidth of the current mirror for this compensation technique. The operation of these circuits has been verified using PSpice simulations for 0.5 ? m CMOS technology at a supply voltage of ±0.75 V.