After the advent of Cu and TiN metallization in high-speed and high-density radio frequency and analog/mixed-signal integrated circuits, new challenges have emerged in achieving low voltage coefficient of capacitance (VCC) in metal-insulation-metal capacitor (MIM) technology. While single layer high-k dielectric MIM capacitors fail to provide low VCC ( $$<100$$ ppm/V $$^{2}$$ ), stacked high-k/ $$\hbox {SiO}_{2}$$ dielectrics show a promising solution as the negative VCC of $$\hbox {SiO}_{2}$$ cancels the positive VCC of high-k materials. To understand the mechanism and origin of negative VCC, a unified analytical model of negative VCC with experimental validation is presented in this paper. This model would be a very useful tool to design high performance MIM capacitors with ultra-low VCC for radio frequency and analog/mixed-signal integrated circuits.